//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-23083092
// Cuda compilation tools, release 9.1, V9.1.85
// Based on LLVM 3.4svn
//

.version 6.1
.target sm_30
.address_size 64

	// .globl	_Z6oxMainv
.global .align 8 .b8 pixelID[8];
.global .align 8 .b8 resolution[8];
.global .align 4 .b8 normal[12];
.global .align 4 .b8 camPos[12];
.global .align 4 .b8 root[4];
.global .align 4 .u32 imageEnabled;
.global .texref lightmap;
.global .align 16 .b8 tileInfo[16];
.global .align 4 .u32 additive;
.global .align 1 .b8 image2[1];
.global .align 1 .b8 image3[1];
.global .align 4 .u32 composeMode;
.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo6normalE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo6camPosE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo4rootE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo12imageEnabledE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo8tileInfoE[8] = {82, 97, 121, 0, 16, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo8additiveE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo11composeModeE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
.global .align 8 .b8 _ZN21rti_internal_typename6normalE[7] = {102, 108, 111, 97, 116, 51, 0};
.global .align 8 .b8 _ZN21rti_internal_typename6camPosE[7] = {102, 108, 111, 97, 116, 51, 0};
.global .align 16 .b8 _ZN21rti_internal_typename4rootE[9] = {114, 116, 79, 98, 106, 101, 99, 116, 0};
.global .align 4 .b8 _ZN21rti_internal_typename12imageEnabledE[4] = {105, 110, 116, 0};
.global .align 8 .b8 _ZN21rti_internal_typename8tileInfoE[6] = {117, 105, 110, 116, 52, 0};
.global .align 4 .b8 _ZN21rti_internal_typename8additiveE[4] = {105, 110, 116, 0};
.global .align 4 .b8 _ZN21rti_internal_typename11composeModeE[4] = {105, 110, 116, 0};
.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum6normalE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum6camPosE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum4rootE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum12imageEnabledE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum8tileInfoE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum8additiveE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum11composeModeE = 4919;
.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
.global .align 16 .b8 _ZN21rti_internal_semantic6normalE[17] = {97, 116, 116, 114, 105, 98, 117, 116, 101, 32, 110, 111, 114, 109, 97, 108, 0};
.global .align 1 .b8 _ZN21rti_internal_semantic6camPosE[1];
.global .align 1 .b8 _ZN21rti_internal_semantic4rootE[1];
.global .align 1 .b8 _ZN21rti_internal_semantic12imageEnabledE[1];
.global .align 1 .b8 _ZN21rti_internal_semantic8tileInfoE[1];
.global .align 1 .b8 _ZN21rti_internal_semantic8additiveE[1];
.global .align 1 .b8 _ZN21rti_internal_semantic11composeModeE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation6normalE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation6camPosE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation4rootE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation12imageEnabledE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation8tileInfoE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation8additiveE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation11composeModeE[1];

.visible .entry _Z6oxMainv(

)
{
	.reg .pred 	%p<52>;
	.reg .b16 	%rs<12>;
	.reg .f32 	%f<334>;
	.reg .b32 	%r<79>;
	.reg .b64 	%rd<55>;


	ld.global.v2.u32 	{%r15, %r16}, [pixelID];
	cvt.u64.u32	%rd3, %r15;
	cvt.u64.u32	%rd4, %r16;
	mov.u64 	%rd43, image2;
	cvta.global.u64 	%rd2, %rd43;
	mov.u32 	%r13, 2;
	mov.u32 	%r8, 8;
	mov.u64 	%rd42, 0;
	// inline asm
	call (%rd1), _rt_buffer_get_64, (%rd2, %r13, %r8, %rd3, %rd4, %rd42, %rd42);
	// inline asm
	ld.u16 	%rs4, [%rd1+6];
	cvt.rn.f32.u16	%f1, %rs4;
	ld.global.v2.u32 	{%r19, %r20}, [pixelID];
	cvt.u64.u32	%rd9, %r19;
	cvt.u64.u32	%rd10, %r20;
	// inline asm
	call (%rd7), _rt_buffer_get_64, (%rd2, %r13, %r8, %rd9, %rd10, %rd42, %rd42);
	// inline asm
	ld.u16 	%rs1, [%rd7];
	// inline asm
	{  cvt.f32.f16 %f47, %rs1;}

	// inline asm
	ld.global.v2.u32 	{%r23, %r24}, [pixelID];
	cvt.u64.u32	%rd15, %r23;
	cvt.u64.u32	%rd16, %r24;
	// inline asm
	call (%rd13), _rt_buffer_get_64, (%rd2, %r13, %r8, %rd15, %rd16, %rd42, %rd42);
	// inline asm
	ld.u16 	%rs2, [%rd13+2];
	// inline asm
	{  cvt.f32.f16 %f48, %rs2;}

	// inline asm
	ld.global.v2.u32 	{%r27, %r28}, [pixelID];
	cvt.u64.u32	%rd21, %r27;
	cvt.u64.u32	%rd22, %r28;
	// inline asm
	call (%rd19), _rt_buffer_get_64, (%rd2, %r13, %r8, %rd21, %rd22, %rd42, %rd42);
	// inline asm
	ld.u16 	%rs3, [%rd19+4];
	// inline asm
	{  cvt.f32.f16 %f49, %rs3;}

	// inline asm
	ld.global.v2.u32 	{%r31, %r32}, [pixelID];
	cvt.u64.u32	%rd27, %r31;
	cvt.u64.u32	%rd28, %r32;
	mov.u64 	%rd44, image3;
	cvta.global.u64 	%rd26, %rd44;
	mov.u32 	%r14, 4;
	// inline asm
	call (%rd25), _rt_buffer_get_64, (%rd26, %r13, %r14, %rd27, %rd28, %rd42, %rd42);
	// inline asm
	ld.u8 	%rs5, [%rd25];
	cvt.rn.f32.u16	%f52, %rs5;
	div.rn.f32 	%f5, %f52, 0f437F0000;
	ld.global.v2.u32 	{%r35, %r36}, [pixelID];
	cvt.u64.u32	%rd33, %r35;
	cvt.u64.u32	%rd34, %r36;
	// inline asm
	call (%rd31), _rt_buffer_get_64, (%rd26, %r13, %r14, %rd33, %rd34, %rd42, %rd42);
	// inline asm
	ld.u8 	%rs6, [%rd31+1];
	cvt.rn.f32.u16	%f53, %rs6;
	div.rn.f32 	%f6, %f53, 0f437F0000;
	ld.global.v2.u32 	{%r39, %r40}, [pixelID];
	cvt.u64.u32	%rd39, %r39;
	cvt.u64.u32	%rd40, %r40;
	// inline asm
	call (%rd37), _rt_buffer_get_64, (%rd26, %r13, %r14, %rd39, %rd40, %rd42, %rd42);
	// inline asm
	ld.u8 	%rs7, [%rd37+2];
	cvt.rn.f32.u16	%f54, %rs7;
	div.rn.f32 	%f7, %f54, 0f437F0000;
	abs.f32 	%f9, %f5;
	setp.lt.f32	%p4, %f9, 0f00800000;
	mul.f32 	%f58, %f9, 0f4B800000;
	selp.f32	%f59, 0fC3170000, 0fC2FE0000, %p4;
	selp.f32	%f60, %f58, %f9, %p4;
	mov.b32 	 %r43, %f60;
	and.b32  	%r44, %r43, 8388607;
	or.b32  	%r45, %r44, 1065353216;
	mov.b32 	 %f61, %r45;
	shr.u32 	%r46, %r43, 23;
	cvt.rn.f32.u32	%f62, %r46;
	add.f32 	%f63, %f59, %f62;
	setp.gt.f32	%p5, %f61, 0f3FB504F3;
	mul.f32 	%f64, %f61, 0f3F000000;
	add.f32 	%f65, %f63, 0f3F800000;
	selp.f32	%f66, %f64, %f61, %p5;
	selp.f32	%f67, %f65, %f63, %p5;
	add.f32 	%f68, %f66, 0fBF800000;
	add.f32 	%f51, %f66, 0f3F800000;
	// inline asm
	rcp.approx.ftz.f32 %f50,%f51;
	// inline asm
	add.f32 	%f69, %f68, %f68;
	mul.f32 	%f70, %f50, %f69;
	mul.f32 	%f71, %f70, %f70;
	mov.f32 	%f72, 0f3C4CAF63;
	mov.f32 	%f73, 0f3B18F0FE;
	fma.rn.f32 	%f74, %f73, %f71, %f72;
	mov.f32 	%f75, 0f3DAAAABD;
	fma.rn.f32 	%f76, %f74, %f71, %f75;
	mul.rn.f32 	%f77, %f76, %f71;
	mul.rn.f32 	%f78, %f77, %f70;
	sub.f32 	%f79, %f68, %f70;
	neg.f32 	%f80, %f70;
	add.f32 	%f81, %f79, %f79;
	fma.rn.f32 	%f82, %f80, %f68, %f81;
	mul.rn.f32 	%f83, %f50, %f82;
	add.f32 	%f84, %f78, %f70;
	sub.f32 	%f85, %f70, %f84;
	add.f32 	%f86, %f78, %f85;
	add.f32 	%f87, %f83, %f86;
	add.f32 	%f88, %f84, %f87;
	sub.f32 	%f89, %f84, %f88;
	add.f32 	%f90, %f87, %f89;
	mov.f32 	%f91, 0f3F317200;
	mul.rn.f32 	%f92, %f67, %f91;
	mov.f32 	%f93, 0f35BFBE8E;
	mul.rn.f32 	%f94, %f67, %f93;
	add.f32 	%f95, %f92, %f88;
	sub.f32 	%f96, %f92, %f95;
	add.f32 	%f97, %f88, %f96;
	add.f32 	%f98, %f90, %f97;
	add.f32 	%f99, %f94, %f98;
	add.f32 	%f100, %f95, %f99;
	sub.f32 	%f101, %f95, %f100;
	add.f32 	%f102, %f99, %f101;
	mov.f32 	%f103, 0f400CCCCD;
	mul.rn.f32 	%f104, %f103, %f100;
	neg.f32 	%f105, %f104;
	fma.rn.f32 	%f106, %f103, %f100, %f105;
	fma.rn.f32 	%f107, %f103, %f102, %f106;
	mov.f32 	%f108, 0f00000000;
	fma.rn.f32 	%f109, %f108, %f100, %f107;
	add.rn.f32 	%f110, %f104, %f109;
	neg.f32 	%f111, %f110;
	add.rn.f32 	%f112, %f104, %f111;
	add.rn.f32 	%f113, %f112, %f109;
	mov.b32 	 %r47, %f110;
	setp.eq.s32	%p6, %r47, 1118925336;
	add.s32 	%r48, %r47, -1;
	mov.b32 	 %f114, %r48;
	add.f32 	%f115, %f113, 0f37000000;
	selp.f32	%f116, %f114, %f110, %p6;
	selp.f32	%f10, %f115, %f113, %p6;
	mul.f32 	%f117, %f116, 0f3FB8AA3B;
	cvt.rzi.f32.f32	%f118, %f117;
	mov.f32 	%f119, 0fBF317200;
	fma.rn.f32 	%f120, %f118, %f119, %f116;
	mov.f32 	%f121, 0fB5BFBE8E;
	fma.rn.f32 	%f122, %f118, %f121, %f120;
	mul.f32 	%f123, %f122, 0f3FB8AA3B;
	ex2.approx.ftz.f32 	%f124, %f123;
	add.f32 	%f125, %f118, 0f00000000;
	ex2.approx.f32 	%f126, %f125;
	mul.f32 	%f127, %f124, %f126;
	setp.lt.f32	%p7, %f116, 0fC2D20000;
	selp.f32	%f128, 0f00000000, %f127, %p7;
	setp.gt.f32	%p8, %f116, 0f42D20000;
	selp.f32	%f325, 0f7F800000, %f128, %p8;
	setp.eq.f32	%p9, %f325, 0f7F800000;
	@%p9 bra 	BB0_2;

	fma.rn.f32 	%f325, %f325, %f10, %f325;

BB0_2:
	mov.f32 	%f322, 0f3F8CCCCD;
	cvt.rzi.f32.f32	%f321, %f322;
	fma.rn.f32 	%f320, %f321, 0fC0000000, 0f400CCCCD;
	abs.f32 	%f319, %f320;
	setp.lt.f32	%p10, %f5, 0f00000000;
	setp.eq.f32	%p11, %f319, 0f3F800000;
	and.pred  	%p1, %p10, %p11;
	mov.b32 	 %r49, %f325;
	xor.b32  	%r50, %r49, -2147483648;
	mov.b32 	 %f129, %r50;
	selp.f32	%f327, %f129, %f325, %p1;
	setp.eq.f32	%p12, %f5, 0f00000000;
	@%p12 bra 	BB0_5;
	bra.uni 	BB0_3;

BB0_5:
	add.f32 	%f132, %f5, %f5;
	selp.f32	%f327, %f132, 0f00000000, %p11;
	bra.uni 	BB0_6;

BB0_3:
	setp.geu.f32	%p13, %f5, 0f00000000;
	@%p13 bra 	BB0_6;

	mov.f32 	%f324, 0f400CCCCD;
	cvt.rzi.f32.f32	%f131, %f324;
	setp.neu.f32	%p14, %f131, 0f400CCCCD;
	selp.f32	%f327, 0f7FFFFFFF, %f327, %p14;

BB0_6:
	abs.f32 	%f294, %f5;
	add.f32 	%f133, %f294, 0f400CCCCD;
	mov.b32 	 %r51, %f133;
	setp.lt.s32	%p16, %r51, 2139095040;
	@%p16 bra 	BB0_11;

	abs.f32 	%f311, %f5;
	setp.gtu.f32	%p17, %f311, 0f7F800000;
	@%p17 bra 	BB0_10;
	bra.uni 	BB0_8;

BB0_10:
	add.f32 	%f327, %f5, 0f400CCCCD;
	bra.uni 	BB0_11;

BB0_8:
	abs.f32 	%f312, %f5;
	setp.neu.f32	%p18, %f312, 0f7F800000;
	@%p18 bra 	BB0_11;

	selp.f32	%f327, 0fFF800000, 0f7F800000, %p1;

BB0_11:
	mov.f32 	%f323, 0f400CCCCD;
	mov.f32 	%f302, 0fB5BFBE8E;
	mov.f32 	%f301, 0fBF317200;
	mov.f32 	%f300, 0f00000000;
	mov.f32 	%f299, 0f35BFBE8E;
	mov.f32 	%f298, 0f3F317200;
	mov.f32 	%f297, 0f3DAAAABD;
	mov.f32 	%f296, 0f3C4CAF63;
	mov.f32 	%f295, 0f3B18F0FE;
	setp.eq.f32	%p19, %f5, 0f3F800000;
	selp.f32	%f21, 0f3F800000, %f327, %p19;
	abs.f32 	%f22, %f6;
	setp.lt.f32	%p20, %f22, 0f00800000;
	mul.f32 	%f136, %f22, 0f4B800000;
	selp.f32	%f137, 0fC3170000, 0fC2FE0000, %p20;
	selp.f32	%f138, %f136, %f22, %p20;
	mov.b32 	 %r52, %f138;
	and.b32  	%r53, %r52, 8388607;
	or.b32  	%r54, %r53, 1065353216;
	mov.b32 	 %f139, %r54;
	shr.u32 	%r55, %r52, 23;
	cvt.rn.f32.u32	%f140, %r55;
	add.f32 	%f141, %f137, %f140;
	setp.gt.f32	%p21, %f139, 0f3FB504F3;
	mul.f32 	%f142, %f139, 0f3F000000;
	add.f32 	%f143, %f141, 0f3F800000;
	selp.f32	%f144, %f142, %f139, %p21;
	selp.f32	%f145, %f143, %f141, %p21;
	add.f32 	%f146, %f144, 0fBF800000;
	add.f32 	%f135, %f144, 0f3F800000;
	// inline asm
	rcp.approx.ftz.f32 %f134,%f135;
	// inline asm
	add.f32 	%f147, %f146, %f146;
	mul.f32 	%f148, %f134, %f147;
	mul.f32 	%f149, %f148, %f148;
	fma.rn.f32 	%f152, %f295, %f149, %f296;
	fma.rn.f32 	%f154, %f152, %f149, %f297;
	mul.rn.f32 	%f155, %f154, %f149;
	mul.rn.f32 	%f156, %f155, %f148;
	sub.f32 	%f157, %f146, %f148;
	neg.f32 	%f158, %f148;
	add.f32 	%f159, %f157, %f157;
	fma.rn.f32 	%f160, %f158, %f146, %f159;
	mul.rn.f32 	%f161, %f134, %f160;
	add.f32 	%f162, %f156, %f148;
	sub.f32 	%f163, %f148, %f162;
	add.f32 	%f164, %f156, %f163;
	add.f32 	%f165, %f161, %f164;
	add.f32 	%f166, %f162, %f165;
	sub.f32 	%f167, %f162, %f166;
	add.f32 	%f168, %f165, %f167;
	mul.rn.f32 	%f170, %f145, %f298;
	mul.rn.f32 	%f172, %f145, %f299;
	add.f32 	%f173, %f170, %f166;
	sub.f32 	%f174, %f170, %f173;
	add.f32 	%f175, %f166, %f174;
	add.f32 	%f176, %f168, %f175;
	add.f32 	%f177, %f172, %f176;
	add.f32 	%f178, %f173, %f177;
	sub.f32 	%f179, %f173, %f178;
	add.f32 	%f180, %f177, %f179;
	mul.rn.f32 	%f182, %f323, %f178;
	neg.f32 	%f183, %f182;
	fma.rn.f32 	%f184, %f323, %f178, %f183;
	fma.rn.f32 	%f185, %f323, %f180, %f184;
	fma.rn.f32 	%f187, %f300, %f178, %f185;
	add.rn.f32 	%f188, %f182, %f187;
	neg.f32 	%f189, %f188;
	add.rn.f32 	%f190, %f182, %f189;
	add.rn.f32 	%f191, %f190, %f187;
	mov.b32 	 %r56, %f188;
	setp.eq.s32	%p22, %r56, 1118925336;
	add.s32 	%r57, %r56, -1;
	mov.b32 	 %f192, %r57;
	add.f32 	%f193, %f191, 0f37000000;
	selp.f32	%f194, %f192, %f188, %p22;
	selp.f32	%f23, %f193, %f191, %p22;
	mul.f32 	%f195, %f194, 0f3FB8AA3B;
	cvt.rzi.f32.f32	%f196, %f195;
	fma.rn.f32 	%f198, %f196, %f301, %f194;
	fma.rn.f32 	%f200, %f196, %f302, %f198;
	mul.f32 	%f201, %f200, 0f3FB8AA3B;
	ex2.approx.ftz.f32 	%f202, %f201;
	add.f32 	%f203, %f196, 0f00000000;
	ex2.approx.f32 	%f204, %f203;
	mul.f32 	%f205, %f202, %f204;
	setp.lt.f32	%p23, %f194, 0fC2D20000;
	selp.f32	%f206, 0f00000000, %f205, %p23;
	setp.gt.f32	%p24, %f194, 0f42D20000;
	selp.f32	%f328, 0f7F800000, %f206, %p24;
	setp.eq.f32	%p25, %f328, 0f7F800000;
	@%p25 bra 	BB0_13;

	fma.rn.f32 	%f328, %f328, %f23, %f328;

BB0_13:
	setp.lt.f32	%p26, %f6, 0f00000000;
	and.pred  	%p2, %p26, %p11;
	mov.b32 	 %r58, %f328;
	xor.b32  	%r59, %r58, -2147483648;
	mov.b32 	 %f207, %r59;
	selp.f32	%f330, %f207, %f328, %p2;
	setp.eq.f32	%p28, %f6, 0f00000000;
	@%p28 bra 	BB0_16;
	bra.uni 	BB0_14;

BB0_16:
	add.f32 	%f210, %f6, %f6;
	selp.f32	%f330, %f210, 0f00000000, %p11;
	bra.uni 	BB0_17;

BB0_14:
	setp.geu.f32	%p29, %f6, 0f00000000;
	@%p29 bra 	BB0_17;

	mov.f32 	%f318, 0f400CCCCD;
	cvt.rzi.f32.f32	%f209, %f318;
	setp.neu.f32	%p30, %f209, 0f400CCCCD;
	selp.f32	%f330, 0f7FFFFFFF, %f330, %p30;

BB0_17:
	abs.f32 	%f313, %f6;
	add.f32 	%f211, %f313, 0f400CCCCD;
	mov.b32 	 %r60, %f211;
	setp.lt.s32	%p32, %r60, 2139095040;
	@%p32 bra 	BB0_22;

	abs.f32 	%f316, %f6;
	setp.gtu.f32	%p33, %f316, 0f7F800000;
	@%p33 bra 	BB0_21;
	bra.uni 	BB0_19;

BB0_21:
	add.f32 	%f330, %f6, 0f400CCCCD;
	bra.uni 	BB0_22;

BB0_19:
	abs.f32 	%f317, %f6;
	setp.neu.f32	%p34, %f317, 0f7F800000;
	@%p34 bra 	BB0_22;

	selp.f32	%f330, 0fFF800000, 0f7F800000, %p2;

BB0_22:
	mov.f32 	%f314, 0f400CCCCD;
	mov.f32 	%f310, 0fB5BFBE8E;
	mov.f32 	%f309, 0fBF317200;
	mov.f32 	%f308, 0f00000000;
	mov.f32 	%f307, 0f35BFBE8E;
	mov.f32 	%f306, 0f3F317200;
	mov.f32 	%f305, 0f3DAAAABD;
	mov.f32 	%f304, 0f3C4CAF63;
	mov.f32 	%f303, 0f3B18F0FE;
	setp.eq.f32	%p35, %f6, 0f3F800000;
	selp.f32	%f34, 0f3F800000, %f330, %p35;
	abs.f32 	%f35, %f7;
	setp.lt.f32	%p36, %f35, 0f00800000;
	mul.f32 	%f214, %f35, 0f4B800000;
	selp.f32	%f215, 0fC3170000, 0fC2FE0000, %p36;
	selp.f32	%f216, %f214, %f35, %p36;
	mov.b32 	 %r61, %f216;
	and.b32  	%r62, %r61, 8388607;
	or.b32  	%r63, %r62, 1065353216;
	mov.b32 	 %f217, %r63;
	shr.u32 	%r64, %r61, 23;
	cvt.rn.f32.u32	%f218, %r64;
	add.f32 	%f219, %f215, %f218;
	setp.gt.f32	%p37, %f217, 0f3FB504F3;
	mul.f32 	%f220, %f217, 0f3F000000;
	add.f32 	%f221, %f219, 0f3F800000;
	selp.f32	%f222, %f220, %f217, %p37;
	selp.f32	%f223, %f221, %f219, %p37;
	add.f32 	%f224, %f222, 0fBF800000;
	add.f32 	%f213, %f222, 0f3F800000;
	// inline asm
	rcp.approx.ftz.f32 %f212,%f213;
	// inline asm
	add.f32 	%f225, %f224, %f224;
	mul.f32 	%f226, %f212, %f225;
	mul.f32 	%f227, %f226, %f226;
	fma.rn.f32 	%f230, %f303, %f227, %f304;
	fma.rn.f32 	%f232, %f230, %f227, %f305;
	mul.rn.f32 	%f233, %f232, %f227;
	mul.rn.f32 	%f234, %f233, %f226;
	sub.f32 	%f235, %f224, %f226;
	neg.f32 	%f236, %f226;
	add.f32 	%f237, %f235, %f235;
	fma.rn.f32 	%f238, %f236, %f224, %f237;
	mul.rn.f32 	%f239, %f212, %f238;
	add.f32 	%f240, %f234, %f226;
	sub.f32 	%f241, %f226, %f240;
	add.f32 	%f242, %f234, %f241;
	add.f32 	%f243, %f239, %f242;
	add.f32 	%f244, %f240, %f243;
	sub.f32 	%f245, %f240, %f244;
	add.f32 	%f246, %f243, %f245;
	mul.rn.f32 	%f248, %f223, %f306;
	mul.rn.f32 	%f250, %f223, %f307;
	add.f32 	%f251, %f248, %f244;
	sub.f32 	%f252, %f248, %f251;
	add.f32 	%f253, %f244, %f252;
	add.f32 	%f254, %f246, %f253;
	add.f32 	%f255, %f250, %f254;
	add.f32 	%f256, %f251, %f255;
	sub.f32 	%f257, %f251, %f256;
	add.f32 	%f258, %f255, %f257;
	mul.rn.f32 	%f260, %f314, %f256;
	neg.f32 	%f261, %f260;
	fma.rn.f32 	%f262, %f314, %f256, %f261;
	fma.rn.f32 	%f263, %f314, %f258, %f262;
	fma.rn.f32 	%f265, %f308, %f256, %f263;
	add.rn.f32 	%f266, %f260, %f265;
	neg.f32 	%f267, %f266;
	add.rn.f32 	%f268, %f260, %f267;
	add.rn.f32 	%f269, %f268, %f265;
	mov.b32 	 %r65, %f266;
	setp.eq.s32	%p38, %r65, 1118925336;
	add.s32 	%r66, %r65, -1;
	mov.b32 	 %f270, %r66;
	add.f32 	%f271, %f269, 0f37000000;
	selp.f32	%f272, %f270, %f266, %p38;
	selp.f32	%f36, %f271, %f269, %p38;
	mul.f32 	%f273, %f272, 0f3FB8AA3B;
	cvt.rzi.f32.f32	%f274, %f273;
	fma.rn.f32 	%f276, %f274, %f309, %f272;
	fma.rn.f32 	%f278, %f274, %f310, %f276;
	mul.f32 	%f279, %f278, 0f3FB8AA3B;
	ex2.approx.ftz.f32 	%f280, %f279;
	add.f32 	%f281, %f274, 0f00000000;
	ex2.approx.f32 	%f282, %f281;
	mul.f32 	%f283, %f280, %f282;
	setp.lt.f32	%p39, %f272, 0fC2D20000;
	selp.f32	%f284, 0f00000000, %f283, %p39;
	setp.gt.f32	%p40, %f272, 0f42D20000;
	selp.f32	%f331, 0f7F800000, %f284, %p40;
	setp.eq.f32	%p41, %f331, 0f7F800000;
	@%p41 bra 	BB0_24;

	fma.rn.f32 	%f331, %f331, %f36, %f331;

BB0_24:
	setp.lt.f32	%p42, %f7, 0f00000000;
	and.pred  	%p3, %p42, %p11;
	mov.b32 	 %r67, %f331;
	xor.b32  	%r68, %r67, -2147483648;
	mov.b32 	 %f285, %r68;
	selp.f32	%f333, %f285, %f331, %p3;
	setp.eq.f32	%p44, %f7, 0f00000000;
	@%p44 bra 	BB0_27;
	bra.uni 	BB0_25;

BB0_27:
	add.f32 	%f288, %f7, %f7;
	selp.f32	%f333, %f288, 0f00000000, %p11;
	bra.uni 	BB0_28;

BB0_25:
	setp.geu.f32	%p45, %f7, 0f00000000;
	@%p45 bra 	BB0_28;

	mov.f32 	%f315, 0f400CCCCD;
	cvt.rzi.f32.f32	%f287, %f315;
	setp.neu.f32	%p46, %f287, 0f400CCCCD;
	selp.f32	%f333, 0f7FFFFFFF, %f333, %p46;

BB0_28:
	add.f32 	%f289, %f35, 0f400CCCCD;
	mov.b32 	 %r69, %f289;
	setp.lt.s32	%p48, %r69, 2139095040;
	@%p48 bra 	BB0_33;

	setp.gtu.f32	%p49, %f35, 0f7F800000;
	@%p49 bra 	BB0_32;
	bra.uni 	BB0_30;

BB0_32:
	add.f32 	%f333, %f7, 0f400CCCCD;
	bra.uni 	BB0_33;

BB0_30:
	setp.neu.f32	%p50, %f35, 0f7F800000;
	@%p50 bra 	BB0_33;

	selp.f32	%f333, 0fFF800000, 0f7F800000, %p3;

BB0_33:
	mov.u64 	%rd54, 0;
	mov.u32 	%r78, 8;
	mov.u32 	%r77, 2;
	mov.u64 	%rd53, image2;
	cvta.global.u64 	%rd52, %rd53;
	setp.eq.f32	%p51, %f7, 0f3F800000;
	selp.f32	%f293, 0f3F800000, %f333, %p51;
	mul.f32 	%f292, %f49, %f293;
	ld.global.v2.u32 	{%r72, %r73}, [pixelID];
	cvt.u64.u32	%rd47, %r72;
	cvt.u64.u32	%rd48, %r73;
	// inline asm
	call (%rd45), _rt_buffer_get_64, (%rd52, %r77, %r78, %rd47, %rd48, %rd54, %rd54);
	// inline asm
	mul.f32 	%f290, %f47, %f21;
	mul.f32 	%f291, %f48, %f34;
	cvt.rzi.u32.f32	%r76, %f1;
	// inline asm
	{  cvt.rn.f16.f32 %rs10, %f292;}

	// inline asm
	// inline asm
	{  cvt.rn.f16.f32 %rs9, %f291;}

	// inline asm
	// inline asm
	{  cvt.rn.f16.f32 %rs8, %f290;}

	// inline asm
	cvt.u16.u32	%rs11, %r76;
	st.v4.u16 	[%rd45], {%rs8, %rs9, %rs10, %rs11};
	ret;
}