//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-23083092
// Cuda compilation tools, release 9.1, V9.1.85
// Based on LLVM 3.4svn
//

.version 6.1
.target sm_30
.address_size 64

	// .globl	_Z6oxMainv
.global .align 8 .b8 pixelID[8];
.global .align 8 .b8 resolution[8];
.global .align 1 .b8 output_buffer[1];
.global .align 1 .b8 image2[1];
.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];

.visible .entry _Z6oxMainv(

)
{
	.reg .b16 	%rs<5>;
	.reg .f32 	%f<5>;
	.reg .b32 	%r<13>;
	.reg .b64 	%rd<15>;


	ld.global.v2.u32 	{%r5, %r6}, [pixelID];
	cvt.u64.u32	%rd3, %r5;
	cvt.u64.u32	%rd4, %r6;
	mov.u64 	%rd13, output_buffer;
	cvta.global.u64 	%rd2, %rd13;
	mov.u32 	%r3, 2;
	mov.u32 	%r2, 12;
	mov.u64 	%rd12, 0;
	// inline asm
	call (%rd1), _rt_buffer_get_64, (%rd2, %r3, %r2, %rd3, %rd4, %rd12, %rd12);
	// inline asm
	ld.f32 	%f1, [%rd1];
	ld.f32 	%f2, [%rd1+4];
	ld.f32 	%f3, [%rd1+8];
	ld.global.v2.u32 	{%r9, %r10}, [pixelID];
	cvt.u64.u32	%rd9, %r9;
	cvt.u64.u32	%rd10, %r10;
	mov.u64 	%rd14, image2;
	cvta.global.u64 	%rd8, %rd14;
	mov.u32 	%r4, 8;
	// inline asm
	call (%rd7), _rt_buffer_get_64, (%rd8, %r3, %r4, %rd9, %rd10, %rd12, %rd12);
	// inline asm
	// inline asm
	{  cvt.rn.f16.f32 %rs3, %f3;}

	// inline asm
	// inline asm
	{  cvt.rn.f16.f32 %rs2, %f2;}

	// inline asm
	// inline asm
	{  cvt.rn.f16.f32 %rs1, %f1;}

	// inline asm
	mov.f32 	%f4, 0f3F800000;
	// inline asm
	{  cvt.rn.f16.f32 %rs4, %f4;}

	// inline asm
	st.v4.u16 	[%rd7], {%rs1, %rs2, %rs3, %rs4};
	ret;
}