587 lines
17 KiB
Plaintext
587 lines
17 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-23083092
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// Cuda compilation tools, release 9.1, V9.1.85
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// Based on LLVM 3.4svn
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//
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.version 6.1
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.target sm_30
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.address_size 64
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// .globl _Z6oxMainv
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.global .align 8 .b8 pixelID[8];
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.global .align 8 .b8 resolution[8];
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.global .align 1 .b8 image[1];
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.global .align 1 .b8 input_buffer[1];
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.global .align 4 .u32 mode;
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.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo4modeE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
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.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
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.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
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.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
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.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
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.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
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.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
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.global .align 4 .b8 _ZN21rti_internal_typename4modeE[4] = {105, 110, 116, 0};
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.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum4modeE = 4919;
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.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
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.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
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.global .align 1 .b8 _ZN21rti_internal_semantic4modeE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation4modeE[1];
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.visible .entry _Z6oxMainv(
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)
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{
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.reg .pred %p<54>;
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.reg .b16 %rs<4>;
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.reg .f32 %f<335>;
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.reg .b32 %r<55>;
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.reg .b64 %rd<29>;
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ld.global.v2.u32 {%r7, %r8}, [pixelID];
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cvt.u64.u32 %rd4, %r7;
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cvt.u64.u32 %rd5, %r8;
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mov.u64 %rd20, image;
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cvta.global.u64 %rd3, %rd20;
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mov.u32 %r5, 2;
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mov.u32 %r6, 8;
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mov.u64 %rd19, 0;
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// inline asm
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call (%rd2), _rt_buffer_get_64, (%rd3, %r5, %r6, %rd4, %rd5, %rd19, %rd19);
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// inline asm
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ld.u16 %rs1, [%rd2];
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// inline asm
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{ cvt.f32.f16 %f44, %rs1;}
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// inline asm
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ld.global.v2.u32 {%r11, %r12}, [pixelID];
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cvt.u64.u32 %rd10, %r11;
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cvt.u64.u32 %rd11, %r12;
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// inline asm
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call (%rd8), _rt_buffer_get_64, (%rd3, %r5, %r6, %rd10, %rd11, %rd19, %rd19);
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// inline asm
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ld.u16 %rs2, [%rd8+2];
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// inline asm
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{ cvt.f32.f16 %f45, %rs2;}
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// inline asm
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ld.global.v2.u32 {%r15, %r16}, [pixelID];
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cvt.u64.u32 %rd16, %r15;
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cvt.u64.u32 %rd17, %r16;
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// inline asm
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call (%rd14), _rt_buffer_get_64, (%rd3, %r5, %r6, %rd16, %rd17, %rd19, %rd19);
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// inline asm
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ld.u16 %rs3, [%rd14+4];
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// inline asm
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{ cvt.f32.f16 %f46, %rs3;}
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// inline asm
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max.f32 %f49, %f44, %f45;
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max.f32 %f50, %f49, %f46;
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add.f32 %f51, %f50, 0f3F800000;
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rcp.rn.f32 %f52, %f51;
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mul.f32 %f53, %f44, %f52;
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mul.f32 %f1, %f45, %f52;
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mul.f32 %f54, %f46, %f52;
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ld.global.u32 %r19, [mode];
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setp.eq.s32 %p4, %r19, 1;
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selp.f32 %f2, %f54, %f53, %p4;
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selp.f32 %f3, %f53, %f54, %p4;
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abs.f32 %f5, %f2;
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setp.lt.f32 %p5, %f5, 0f00800000;
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mul.f32 %f58, %f5, 0f4B800000;
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selp.f32 %f59, 0fC3170000, 0fC2FE0000, %p5;
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selp.f32 %f60, %f58, %f5, %p5;
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mov.b32 %r20, %f60;
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and.b32 %r21, %r20, 8388607;
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or.b32 %r22, %r21, 1065353216;
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mov.b32 %f61, %r22;
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shr.u32 %r23, %r20, 23;
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cvt.rn.f32.u32 %f62, %r23;
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add.f32 %f63, %f59, %f62;
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setp.gt.f32 %p6, %f61, 0f3FB504F3;
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mul.f32 %f64, %f61, 0f3F000000;
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add.f32 %f65, %f63, 0f3F800000;
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selp.f32 %f66, %f64, %f61, %p6;
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selp.f32 %f67, %f65, %f63, %p6;
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add.f32 %f68, %f66, 0fBF800000;
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add.f32 %f48, %f66, 0f3F800000;
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// inline asm
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rcp.approx.ftz.f32 %f47,%f48;
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// inline asm
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add.f32 %f69, %f68, %f68;
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mul.f32 %f70, %f47, %f69;
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mul.f32 %f71, %f70, %f70;
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mov.f32 %f72, 0f3C4CAF63;
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mov.f32 %f73, 0f3B18F0FE;
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fma.rn.f32 %f74, %f73, %f71, %f72;
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mov.f32 %f75, 0f3DAAAABD;
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fma.rn.f32 %f76, %f74, %f71, %f75;
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mul.rn.f32 %f77, %f76, %f71;
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mul.rn.f32 %f78, %f77, %f70;
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sub.f32 %f79, %f68, %f70;
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neg.f32 %f80, %f70;
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add.f32 %f81, %f79, %f79;
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fma.rn.f32 %f82, %f80, %f68, %f81;
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mul.rn.f32 %f83, %f47, %f82;
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add.f32 %f84, %f78, %f70;
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sub.f32 %f85, %f70, %f84;
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add.f32 %f86, %f78, %f85;
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add.f32 %f87, %f83, %f86;
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add.f32 %f88, %f84, %f87;
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sub.f32 %f89, %f84, %f88;
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add.f32 %f90, %f87, %f89;
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mov.f32 %f91, 0f3F317200;
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mul.rn.f32 %f92, %f67, %f91;
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mov.f32 %f93, 0f35BFBE8E;
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mul.rn.f32 %f94, %f67, %f93;
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add.f32 %f95, %f92, %f88;
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sub.f32 %f96, %f92, %f95;
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add.f32 %f97, %f88, %f96;
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add.f32 %f98, %f90, %f97;
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add.f32 %f99, %f94, %f98;
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add.f32 %f100, %f95, %f99;
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sub.f32 %f101, %f95, %f100;
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add.f32 %f102, %f99, %f101;
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mov.f32 %f103, 0f3EE8BA2E;
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mul.rn.f32 %f104, %f103, %f100;
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neg.f32 %f105, %f104;
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fma.rn.f32 %f106, %f103, %f100, %f105;
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fma.rn.f32 %f107, %f103, %f102, %f106;
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mov.f32 %f108, 0f00000000;
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fma.rn.f32 %f109, %f108, %f100, %f107;
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add.rn.f32 %f110, %f104, %f109;
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neg.f32 %f111, %f110;
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add.rn.f32 %f112, %f104, %f111;
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add.rn.f32 %f113, %f112, %f109;
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mov.b32 %r24, %f110;
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setp.eq.s32 %p7, %r24, 1118925336;
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add.s32 %r25, %r24, -1;
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mov.b32 %f114, %r25;
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add.f32 %f115, %f113, 0f37000000;
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selp.f32 %f116, %f114, %f110, %p7;
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selp.f32 %f6, %f115, %f113, %p7;
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mul.f32 %f117, %f116, 0f3FB8AA3B;
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cvt.rzi.f32.f32 %f118, %f117;
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mov.f32 %f119, 0fBF317200;
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fma.rn.f32 %f120, %f118, %f119, %f116;
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mov.f32 %f121, 0fB5BFBE8E;
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fma.rn.f32 %f122, %f118, %f121, %f120;
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mul.f32 %f123, %f122, 0f3FB8AA3B;
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ex2.approx.ftz.f32 %f124, %f123;
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add.f32 %f125, %f118, 0f00000000;
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ex2.approx.f32 %f126, %f125;
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mul.f32 %f127, %f124, %f126;
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setp.lt.f32 %p8, %f116, 0fC2D20000;
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selp.f32 %f128, 0f00000000, %f127, %p8;
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setp.gt.f32 %p9, %f116, 0f42D20000;
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selp.f32 %f326, 0f7F800000, %f128, %p9;
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setp.eq.f32 %p10, %f326, 0f7F800000;
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@%p10 bra BB0_2;
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fma.rn.f32 %f326, %f326, %f6, %f326;
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BB0_2:
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mov.f32 %f325, 0f3E68BA2E;
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cvt.rzi.f32.f32 %f324, %f325;
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fma.rn.f32 %f323, %f324, 0fC0000000, 0f3EE8BA2E;
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abs.f32 %f322, %f323;
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setp.lt.f32 %p11, %f2, 0f00000000;
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setp.eq.f32 %p12, %f322, 0f3F800000;
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and.pred %p1, %p11, %p12;
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mov.b32 %r26, %f326;
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xor.b32 %r27, %r26, -2147483648;
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mov.b32 %f129, %r27;
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selp.f32 %f328, %f129, %f326, %p1;
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setp.eq.f32 %p13, %f2, 0f00000000;
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@%p13 bra BB0_5;
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bra.uni BB0_3;
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BB0_5:
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add.f32 %f132, %f2, %f2;
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selp.f32 %f328, %f132, 0f00000000, %p12;
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bra.uni BB0_6;
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BB0_3:
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setp.geu.f32 %p14, %f2, 0f00000000;
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@%p14 bra BB0_6;
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mov.f32 %f321, 0f3EE8BA2E;
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cvt.rzi.f32.f32 %f131, %f321;
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setp.neu.f32 %p15, %f131, 0f3EE8BA2E;
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selp.f32 %f328, 0f7FFFFFFF, %f328, %p15;
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BB0_6:
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abs.f32 %f298, %f2;
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add.f32 %f133, %f298, 0f3EE8BA2E;
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mov.b32 %r28, %f133;
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setp.lt.s32 %p17, %r28, 2139095040;
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@%p17 bra BB0_11;
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abs.f32 %f319, %f2;
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setp.gtu.f32 %p18, %f319, 0f7F800000;
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@%p18 bra BB0_10;
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bra.uni BB0_8;
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BB0_10:
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add.f32 %f328, %f2, 0f3EE8BA2E;
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bra.uni BB0_11;
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BB0_8:
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abs.f32 %f320, %f2;
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setp.neu.f32 %p19, %f320, 0f7F800000;
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@%p19 bra BB0_11;
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selp.f32 %f328, 0fFF800000, 0f7F800000, %p1;
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BB0_11:
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mov.f32 %f307, 0fB5BFBE8E;
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mov.f32 %f306, 0fBF317200;
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mov.f32 %f305, 0f00000000;
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mov.f32 %f304, 0f35BFBE8E;
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mov.f32 %f303, 0f3F317200;
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mov.f32 %f302, 0f3DAAAABD;
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mov.f32 %f301, 0f3C4CAF63;
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mov.f32 %f300, 0f3B18F0FE;
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mov.f32 %f299, 0f3EE8BA2E;
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setp.eq.f32 %p20, %f2, 0f3F800000;
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selp.f32 %f136, 0f3F800000, %f328, %p20;
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cvt.sat.f32.f32 %f17, %f136;
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abs.f32 %f18, %f1;
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setp.lt.f32 %p21, %f18, 0f00800000;
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mul.f32 %f137, %f18, 0f4B800000;
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selp.f32 %f138, 0fC3170000, 0fC2FE0000, %p21;
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selp.f32 %f139, %f137, %f18, %p21;
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mov.b32 %r29, %f139;
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and.b32 %r30, %r29, 8388607;
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or.b32 %r31, %r30, 1065353216;
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mov.b32 %f140, %r31;
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shr.u32 %r32, %r29, 23;
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cvt.rn.f32.u32 %f141, %r32;
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add.f32 %f142, %f138, %f141;
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setp.gt.f32 %p22, %f140, 0f3FB504F3;
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mul.f32 %f143, %f140, 0f3F000000;
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add.f32 %f144, %f142, 0f3F800000;
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selp.f32 %f145, %f143, %f140, %p22;
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selp.f32 %f146, %f144, %f142, %p22;
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add.f32 %f147, %f145, 0fBF800000;
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add.f32 %f135, %f145, 0f3F800000;
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// inline asm
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rcp.approx.ftz.f32 %f134,%f135;
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// inline asm
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add.f32 %f148, %f147, %f147;
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mul.f32 %f149, %f134, %f148;
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mul.f32 %f150, %f149, %f149;
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fma.rn.f32 %f153, %f300, %f150, %f301;
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fma.rn.f32 %f155, %f153, %f150, %f302;
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mul.rn.f32 %f156, %f155, %f150;
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mul.rn.f32 %f157, %f156, %f149;
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sub.f32 %f158, %f147, %f149;
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neg.f32 %f159, %f149;
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add.f32 %f160, %f158, %f158;
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fma.rn.f32 %f161, %f159, %f147, %f160;
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mul.rn.f32 %f162, %f134, %f161;
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add.f32 %f163, %f157, %f149;
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sub.f32 %f164, %f149, %f163;
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add.f32 %f165, %f157, %f164;
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add.f32 %f166, %f162, %f165;
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add.f32 %f167, %f163, %f166;
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sub.f32 %f168, %f163, %f167;
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add.f32 %f169, %f166, %f168;
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mul.rn.f32 %f171, %f146, %f303;
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mul.rn.f32 %f173, %f146, %f304;
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add.f32 %f174, %f171, %f167;
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sub.f32 %f175, %f171, %f174;
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add.f32 %f176, %f167, %f175;
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add.f32 %f177, %f169, %f176;
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add.f32 %f178, %f173, %f177;
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add.f32 %f179, %f174, %f178;
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sub.f32 %f180, %f174, %f179;
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add.f32 %f181, %f178, %f180;
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mul.rn.f32 %f183, %f299, %f179;
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neg.f32 %f184, %f183;
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fma.rn.f32 %f185, %f299, %f179, %f184;
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fma.rn.f32 %f186, %f299, %f181, %f185;
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fma.rn.f32 %f188, %f305, %f179, %f186;
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add.rn.f32 %f189, %f183, %f188;
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neg.f32 %f190, %f189;
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add.rn.f32 %f191, %f183, %f190;
|
|
add.rn.f32 %f192, %f191, %f188;
|
|
mov.b32 %r33, %f189;
|
|
setp.eq.s32 %p23, %r33, 1118925336;
|
|
add.s32 %r34, %r33, -1;
|
|
mov.b32 %f193, %r34;
|
|
add.f32 %f194, %f192, 0f37000000;
|
|
selp.f32 %f195, %f193, %f189, %p23;
|
|
selp.f32 %f19, %f194, %f192, %p23;
|
|
mul.f32 %f196, %f195, 0f3FB8AA3B;
|
|
cvt.rzi.f32.f32 %f197, %f196;
|
|
fma.rn.f32 %f199, %f197, %f306, %f195;
|
|
fma.rn.f32 %f201, %f197, %f307, %f199;
|
|
mul.f32 %f202, %f201, 0f3FB8AA3B;
|
|
ex2.approx.ftz.f32 %f203, %f202;
|
|
add.f32 %f204, %f197, 0f00000000;
|
|
ex2.approx.f32 %f205, %f204;
|
|
mul.f32 %f206, %f203, %f205;
|
|
setp.lt.f32 %p24, %f195, 0fC2D20000;
|
|
selp.f32 %f207, 0f00000000, %f206, %p24;
|
|
setp.gt.f32 %p25, %f195, 0f42D20000;
|
|
selp.f32 %f329, 0f7F800000, %f207, %p25;
|
|
setp.eq.f32 %p26, %f329, 0f7F800000;
|
|
@%p26 bra BB0_13;
|
|
|
|
fma.rn.f32 %f329, %f329, %f19, %f329;
|
|
|
|
BB0_13:
|
|
setp.lt.f32 %p27, %f1, 0f00000000;
|
|
and.pred %p2, %p27, %p12;
|
|
mov.b32 %r35, %f329;
|
|
xor.b32 %r36, %r35, -2147483648;
|
|
mov.b32 %f208, %r36;
|
|
selp.f32 %f331, %f208, %f329, %p2;
|
|
setp.eq.f32 %p29, %f1, 0f00000000;
|
|
@%p29 bra BB0_16;
|
|
bra.uni BB0_14;
|
|
|
|
BB0_16:
|
|
add.f32 %f211, %f1, %f1;
|
|
selp.f32 %f331, %f211, 0f00000000, %p12;
|
|
bra.uni BB0_17;
|
|
|
|
BB0_14:
|
|
setp.geu.f32 %p30, %f1, 0f00000000;
|
|
@%p30 bra BB0_17;
|
|
|
|
mov.f32 %f318, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f210, %f318;
|
|
setp.neu.f32 %p31, %f210, 0f3EE8BA2E;
|
|
selp.f32 %f331, 0f7FFFFFFF, %f331, %p31;
|
|
|
|
BB0_17:
|
|
add.f32 %f212, %f18, 0f3EE8BA2E;
|
|
mov.b32 %r37, %f212;
|
|
setp.lt.s32 %p33, %r37, 2139095040;
|
|
@%p33 bra BB0_22;
|
|
|
|
setp.gtu.f32 %p34, %f18, 0f7F800000;
|
|
@%p34 bra BB0_21;
|
|
bra.uni BB0_19;
|
|
|
|
BB0_21:
|
|
add.f32 %f331, %f1, 0f3EE8BA2E;
|
|
bra.uni BB0_22;
|
|
|
|
BB0_19:
|
|
setp.neu.f32 %p35, %f18, 0f7F800000;
|
|
@%p35 bra BB0_22;
|
|
|
|
selp.f32 %f331, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
BB0_22:
|
|
mov.f32 %f316, 0fB5BFBE8E;
|
|
mov.f32 %f315, 0fBF317200;
|
|
mov.f32 %f314, 0f00000000;
|
|
mov.f32 %f313, 0f35BFBE8E;
|
|
mov.f32 %f312, 0f3F317200;
|
|
mov.f32 %f311, 0f3DAAAABD;
|
|
mov.f32 %f310, 0f3C4CAF63;
|
|
mov.f32 %f309, 0f3B18F0FE;
|
|
mov.f32 %f308, 0f3EE8BA2E;
|
|
setp.eq.f32 %p36, %f1, 0f3F800000;
|
|
selp.f32 %f215, 0f3F800000, %f331, %p36;
|
|
cvt.sat.f32.f32 %f30, %f215;
|
|
abs.f32 %f31, %f3;
|
|
setp.lt.f32 %p37, %f31, 0f00800000;
|
|
mul.f32 %f216, %f31, 0f4B800000;
|
|
selp.f32 %f217, 0fC3170000, 0fC2FE0000, %p37;
|
|
selp.f32 %f218, %f216, %f31, %p37;
|
|
mov.b32 %r38, %f218;
|
|
and.b32 %r39, %r38, 8388607;
|
|
or.b32 %r40, %r39, 1065353216;
|
|
mov.b32 %f219, %r40;
|
|
shr.u32 %r41, %r38, 23;
|
|
cvt.rn.f32.u32 %f220, %r41;
|
|
add.f32 %f221, %f217, %f220;
|
|
setp.gt.f32 %p38, %f219, 0f3FB504F3;
|
|
mul.f32 %f222, %f219, 0f3F000000;
|
|
add.f32 %f223, %f221, 0f3F800000;
|
|
selp.f32 %f224, %f222, %f219, %p38;
|
|
selp.f32 %f225, %f223, %f221, %p38;
|
|
add.f32 %f226, %f224, 0fBF800000;
|
|
add.f32 %f214, %f224, 0f3F800000;
|
|
// inline asm
|
|
rcp.approx.ftz.f32 %f213,%f214;
|
|
// inline asm
|
|
add.f32 %f227, %f226, %f226;
|
|
mul.f32 %f228, %f213, %f227;
|
|
mul.f32 %f229, %f228, %f228;
|
|
fma.rn.f32 %f232, %f309, %f229, %f310;
|
|
fma.rn.f32 %f234, %f232, %f229, %f311;
|
|
mul.rn.f32 %f235, %f234, %f229;
|
|
mul.rn.f32 %f236, %f235, %f228;
|
|
sub.f32 %f237, %f226, %f228;
|
|
neg.f32 %f238, %f228;
|
|
add.f32 %f239, %f237, %f237;
|
|
fma.rn.f32 %f240, %f238, %f226, %f239;
|
|
mul.rn.f32 %f241, %f213, %f240;
|
|
add.f32 %f242, %f236, %f228;
|
|
sub.f32 %f243, %f228, %f242;
|
|
add.f32 %f244, %f236, %f243;
|
|
add.f32 %f245, %f241, %f244;
|
|
add.f32 %f246, %f242, %f245;
|
|
sub.f32 %f247, %f242, %f246;
|
|
add.f32 %f248, %f245, %f247;
|
|
mul.rn.f32 %f250, %f225, %f312;
|
|
mul.rn.f32 %f252, %f225, %f313;
|
|
add.f32 %f253, %f250, %f246;
|
|
sub.f32 %f254, %f250, %f253;
|
|
add.f32 %f255, %f246, %f254;
|
|
add.f32 %f256, %f248, %f255;
|
|
add.f32 %f257, %f252, %f256;
|
|
add.f32 %f258, %f253, %f257;
|
|
sub.f32 %f259, %f253, %f258;
|
|
add.f32 %f260, %f257, %f259;
|
|
mul.rn.f32 %f262, %f308, %f258;
|
|
neg.f32 %f263, %f262;
|
|
fma.rn.f32 %f264, %f308, %f258, %f263;
|
|
fma.rn.f32 %f265, %f308, %f260, %f264;
|
|
fma.rn.f32 %f267, %f314, %f258, %f265;
|
|
add.rn.f32 %f268, %f262, %f267;
|
|
neg.f32 %f269, %f268;
|
|
add.rn.f32 %f270, %f262, %f269;
|
|
add.rn.f32 %f271, %f270, %f267;
|
|
mov.b32 %r42, %f268;
|
|
setp.eq.s32 %p39, %r42, 1118925336;
|
|
add.s32 %r43, %r42, -1;
|
|
mov.b32 %f272, %r43;
|
|
add.f32 %f273, %f271, 0f37000000;
|
|
selp.f32 %f274, %f272, %f268, %p39;
|
|
selp.f32 %f32, %f273, %f271, %p39;
|
|
mul.f32 %f275, %f274, 0f3FB8AA3B;
|
|
cvt.rzi.f32.f32 %f276, %f275;
|
|
fma.rn.f32 %f278, %f276, %f315, %f274;
|
|
fma.rn.f32 %f280, %f276, %f316, %f278;
|
|
mul.f32 %f281, %f280, 0f3FB8AA3B;
|
|
ex2.approx.ftz.f32 %f282, %f281;
|
|
add.f32 %f283, %f276, 0f00000000;
|
|
ex2.approx.f32 %f284, %f283;
|
|
mul.f32 %f285, %f282, %f284;
|
|
setp.lt.f32 %p40, %f274, 0fC2D20000;
|
|
selp.f32 %f286, 0f00000000, %f285, %p40;
|
|
setp.gt.f32 %p41, %f274, 0f42D20000;
|
|
selp.f32 %f332, 0f7F800000, %f286, %p41;
|
|
setp.eq.f32 %p42, %f332, 0f7F800000;
|
|
@%p42 bra BB0_24;
|
|
|
|
fma.rn.f32 %f332, %f332, %f32, %f332;
|
|
|
|
BB0_24:
|
|
setp.lt.f32 %p43, %f3, 0f00000000;
|
|
and.pred %p3, %p43, %p12;
|
|
mov.b32 %r44, %f332;
|
|
xor.b32 %r45, %r44, -2147483648;
|
|
mov.b32 %f287, %r45;
|
|
selp.f32 %f334, %f287, %f332, %p3;
|
|
setp.eq.f32 %p45, %f3, 0f00000000;
|
|
@%p45 bra BB0_27;
|
|
bra.uni BB0_25;
|
|
|
|
BB0_27:
|
|
add.f32 %f290, %f3, %f3;
|
|
selp.f32 %f334, %f290, 0f00000000, %p12;
|
|
bra.uni BB0_28;
|
|
|
|
BB0_25:
|
|
setp.geu.f32 %p46, %f3, 0f00000000;
|
|
@%p46 bra BB0_28;
|
|
|
|
mov.f32 %f317, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f289, %f317;
|
|
setp.neu.f32 %p47, %f289, 0f3EE8BA2E;
|
|
selp.f32 %f334, 0f7FFFFFFF, %f334, %p47;
|
|
|
|
BB0_28:
|
|
add.f32 %f291, %f31, 0f3EE8BA2E;
|
|
mov.b32 %r46, %f291;
|
|
setp.lt.s32 %p49, %r46, 2139095040;
|
|
@%p49 bra BB0_33;
|
|
|
|
setp.gtu.f32 %p50, %f31, 0f7F800000;
|
|
@%p50 bra BB0_32;
|
|
bra.uni BB0_30;
|
|
|
|
BB0_32:
|
|
add.f32 %f334, %f3, 0f3EE8BA2E;
|
|
bra.uni BB0_33;
|
|
|
|
BB0_30:
|
|
setp.neu.f32 %p51, %f31, 0f7F800000;
|
|
@%p51 bra BB0_33;
|
|
|
|
selp.f32 %f334, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
BB0_33:
|
|
mov.u64 %rd28, 0;
|
|
mov.u32 %r54, 2;
|
|
setp.eq.f32 %p52, %f3, 0f3F800000;
|
|
selp.f32 %f292, 0f3F800000, %f334, %p52;
|
|
cvt.sat.f32.f32 %f43, %f292;
|
|
ld.global.v2.u32 {%r49, %r50}, [pixelID];
|
|
cvt.u64.u32 %rd23, %r49;
|
|
cvt.u64.u32 %rd24, %r50;
|
|
mov.u64 %rd27, input_buffer;
|
|
cvta.global.u64 %rd22, %rd27;
|
|
mov.u32 %r48, 16;
|
|
// inline asm
|
|
call (%rd21), _rt_buffer_get_64, (%rd22, %r54, %r48, %rd23, %rd24, %rd28, %rd28);
|
|
// inline asm
|
|
ld.global.u32 %r53, [mode];
|
|
setp.eq.s32 %p53, %r53, 0;
|
|
@%p53 bra BB0_35;
|
|
|
|
mov.f32 %f293, 0f3F800000;
|
|
sub.f32 %f294, %f293, %f43;
|
|
sub.f32 %f295, %f293, %f30;
|
|
sub.f32 %f296, %f293, %f17;
|
|
st.v4.f32 [%rd21], {%f296, %f295, %f294, %f293};
|
|
bra.uni BB0_36;
|
|
|
|
BB0_35:
|
|
mov.f32 %f297, 0f3F800000;
|
|
st.v4.f32 [%rd21], {%f17, %f30, %f43, %f297};
|
|
|
|
BB0_36:
|
|
ret;
|
|
}
|
|
|
|
|