1051 lines
30 KiB
Plaintext
1051 lines
30 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-23083092
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// Cuda compilation tools, release 9.1, V9.1.85
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// Based on LLVM 3.4svn
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//
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.version 6.1
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.target sm_30
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.address_size 64
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// .globl _Z6oxMainv
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.global .align 8 .b8 pixelID[8];
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.global .align 8 .b8 resolution[8];
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.global .align 1 .b8 output_buffer[1];
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.global .align 1 .b8 image2[1];
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.global .align 4 .u32 mode;
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.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo4modeE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
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.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
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.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
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.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
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.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
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.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
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.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
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.global .align 4 .b8 _ZN21rti_internal_typename4modeE[4] = {105, 110, 116, 0};
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.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum4modeE = 4919;
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.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
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.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
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.global .align 1 .b8 _ZN21rti_internal_semantic4modeE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation4modeE[1];
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.visible .entry _Z6oxMainv(
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)
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{
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.reg .pred %p<105>;
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.reg .b16 %rs<8>;
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.reg .f32 %f<669>;
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.reg .b32 %r<87>;
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.reg .b64 %rd<35>;
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ld.global.v2.u32 {%r3, %r4}, [pixelID];
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cvt.u64.u32 %rd3, %r3;
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cvt.u64.u32 %rd4, %r4;
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mov.u64 %rd7, output_buffer;
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cvta.global.u64 %rd2, %rd7;
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mov.u32 %r1, 2;
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mov.u32 %r2, 16;
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mov.u64 %rd6, 0;
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// inline asm
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call (%rd1), _rt_buffer_get_64, (%rd2, %r1, %r2, %rd3, %rd4, %rd6, %rd6);
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// inline asm
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ld.v4.f32 {%f96, %f97, %f98, %f99}, [%rd1];
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ld.global.u32 %r7, [mode];
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setp.eq.s32 %p7, %r7, 1;
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selp.f32 %f2, %f98, %f96, %p7;
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selp.f32 %f3, %f96, %f98, %p7;
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setp.eq.s32 %p8, %r7, 0;
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mov.f32 %f102, 0f3F8CCCCD;
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cvt.rzi.f32.f32 %f103, %f102;
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fma.rn.f32 %f104, %f103, 0fC0000000, 0f400CCCCD;
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abs.f32 %f4, %f104;
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@%p8 bra BB0_35;
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ld.global.v2.u32 {%r14, %r15}, [pixelID];
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cvt.u64.u32 %rd10, %r14;
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cvt.u64.u32 %rd11, %r15;
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mov.u64 %rd26, image2;
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cvta.global.u64 %rd9, %rd26;
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mov.u32 %r13, 8;
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// inline asm
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call (%rd8), _rt_buffer_get_64, (%rd9, %r1, %r13, %rd10, %rd11, %rd6, %rd6);
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// inline asm
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ld.u16 %rs1, [%rd8];
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// inline asm
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{ cvt.f32.f16 %f105, %rs1;}
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// inline asm
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ld.global.v2.u32 {%r18, %r19}, [pixelID];
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cvt.u64.u32 %rd16, %r18;
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cvt.u64.u32 %rd17, %r19;
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// inline asm
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call (%rd14), _rt_buffer_get_64, (%rd9, %r1, %r13, %rd16, %rd17, %rd6, %rd6);
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// inline asm
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ld.u16 %rs2, [%rd14+2];
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// inline asm
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{ cvt.f32.f16 %f106, %rs2;}
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// inline asm
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ld.global.v2.u32 {%r22, %r23}, [pixelID];
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cvt.u64.u32 %rd22, %r22;
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cvt.u64.u32 %rd23, %r23;
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// inline asm
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call (%rd20), _rt_buffer_get_64, (%rd9, %r1, %r13, %rd22, %rd23, %rd6, %rd6);
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// inline asm
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ld.u16 %rs3, [%rd20+4];
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// inline asm
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{ cvt.f32.f16 %f107, %rs3;}
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// inline asm
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mov.f32 %f110, 0f3F800000;
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sub.f32 %f8, %f110, %f2;
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abs.f32 %f9, %f8;
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setp.lt.f32 %p9, %f9, 0f00800000;
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mul.f32 %f111, %f9, 0f4B800000;
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selp.f32 %f112, 0fC3170000, 0fC2FE0000, %p9;
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selp.f32 %f113, %f111, %f9, %p9;
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mov.b32 %r26, %f113;
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and.b32 %r27, %r26, 8388607;
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or.b32 %r28, %r27, 1065353216;
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mov.b32 %f114, %r28;
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shr.u32 %r29, %r26, 23;
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cvt.rn.f32.u32 %f115, %r29;
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add.f32 %f116, %f112, %f115;
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setp.gt.f32 %p10, %f114, 0f3FB504F3;
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mul.f32 %f117, %f114, 0f3F000000;
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add.f32 %f118, %f116, 0f3F800000;
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selp.f32 %f119, %f117, %f114, %p10;
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selp.f32 %f120, %f118, %f116, %p10;
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add.f32 %f121, %f119, 0fBF800000;
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add.f32 %f109, %f119, 0f3F800000;
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// inline asm
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rcp.approx.ftz.f32 %f108,%f109;
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// inline asm
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add.f32 %f122, %f121, %f121;
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mul.f32 %f123, %f108, %f122;
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mul.f32 %f124, %f123, %f123;
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mov.f32 %f125, 0f3C4CAF63;
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mov.f32 %f126, 0f3B18F0FE;
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fma.rn.f32 %f127, %f126, %f124, %f125;
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mov.f32 %f128, 0f3DAAAABD;
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fma.rn.f32 %f129, %f127, %f124, %f128;
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mul.rn.f32 %f130, %f129, %f124;
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mul.rn.f32 %f131, %f130, %f123;
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sub.f32 %f132, %f121, %f123;
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neg.f32 %f133, %f123;
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add.f32 %f134, %f132, %f132;
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fma.rn.f32 %f135, %f133, %f121, %f134;
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mul.rn.f32 %f136, %f108, %f135;
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add.f32 %f137, %f131, %f123;
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sub.f32 %f138, %f123, %f137;
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add.f32 %f139, %f131, %f138;
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add.f32 %f140, %f136, %f139;
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add.f32 %f141, %f137, %f140;
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sub.f32 %f142, %f137, %f141;
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add.f32 %f143, %f140, %f142;
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mov.f32 %f144, 0f3F317200;
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mul.rn.f32 %f145, %f120, %f144;
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mov.f32 %f146, 0f35BFBE8E;
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mul.rn.f32 %f147, %f120, %f146;
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add.f32 %f148, %f145, %f141;
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sub.f32 %f149, %f145, %f148;
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add.f32 %f150, %f141, %f149;
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add.f32 %f151, %f143, %f150;
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add.f32 %f152, %f147, %f151;
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add.f32 %f153, %f148, %f152;
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sub.f32 %f154, %f148, %f153;
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add.f32 %f155, %f152, %f154;
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mov.f32 %f156, 0f400CCCCD;
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mul.rn.f32 %f157, %f156, %f153;
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neg.f32 %f158, %f157;
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fma.rn.f32 %f159, %f156, %f153, %f158;
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fma.rn.f32 %f160, %f156, %f155, %f159;
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mov.f32 %f161, 0f00000000;
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fma.rn.f32 %f162, %f161, %f153, %f160;
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add.rn.f32 %f163, %f157, %f162;
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neg.f32 %f164, %f163;
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add.rn.f32 %f165, %f157, %f164;
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add.rn.f32 %f166, %f165, %f162;
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mov.b32 %r30, %f163;
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setp.eq.s32 %p11, %r30, 1118925336;
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add.s32 %r31, %r30, -1;
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mov.b32 %f167, %r31;
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add.f32 %f168, %f166, 0f37000000;
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selp.f32 %f169, %f167, %f163, %p11;
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selp.f32 %f10, %f168, %f166, %p11;
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mul.f32 %f170, %f169, 0f3FB8AA3B;
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cvt.rzi.f32.f32 %f171, %f170;
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mov.f32 %f172, 0fBF317200;
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fma.rn.f32 %f173, %f171, %f172, %f169;
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mov.f32 %f174, 0fB5BFBE8E;
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fma.rn.f32 %f175, %f171, %f174, %f173;
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mul.f32 %f176, %f175, 0f3FB8AA3B;
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ex2.approx.ftz.f32 %f177, %f176;
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add.f32 %f178, %f171, 0f00000000;
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ex2.approx.f32 %f179, %f178;
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mul.f32 %f180, %f177, %f179;
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setp.lt.f32 %p12, %f169, 0fC2D20000;
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selp.f32 %f181, 0f00000000, %f180, %p12;
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setp.gt.f32 %p13, %f169, 0f42D20000;
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selp.f32 %f648, 0f7F800000, %f181, %p13;
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setp.eq.f32 %p14, %f648, 0f7F800000;
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@%p14 bra BB0_3;
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fma.rn.f32 %f648, %f648, %f10, %f648;
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BB0_3:
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setp.lt.f32 %p15, %f8, 0f00000000;
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setp.eq.f32 %p16, %f4, 0f3F800000;
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and.pred %p1, %p15, %p16;
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mov.b32 %r32, %f648;
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xor.b32 %r33, %r32, -2147483648;
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mov.b32 %f182, %r33;
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selp.f32 %f650, %f182, %f648, %p1;
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setp.eq.f32 %p17, %f8, 0f00000000;
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@%p17 bra BB0_6;
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bra.uni BB0_4;
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BB0_6:
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add.f32 %f185, %f8, %f8;
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selp.f32 %f650, %f185, 0f00000000, %p16;
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bra.uni BB0_7;
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BB0_35:
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abs.f32 %f52, %f2;
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setp.lt.f32 %p57, %f52, 0f00800000;
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mul.f32 %f359, %f52, 0f4B800000;
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selp.f32 %f360, 0fC3170000, 0fC2FE0000, %p57;
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selp.f32 %f361, %f359, %f52, %p57;
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mov.b32 %r53, %f361;
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and.b32 %r54, %r53, 8388607;
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or.b32 %r55, %r54, 1065353216;
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mov.b32 %f362, %r55;
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shr.u32 %r56, %r53, 23;
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cvt.rn.f32.u32 %f363, %r56;
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add.f32 %f364, %f360, %f363;
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setp.gt.f32 %p58, %f362, 0f3FB504F3;
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mul.f32 %f365, %f362, 0f3F000000;
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add.f32 %f366, %f364, 0f3F800000;
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selp.f32 %f367, %f365, %f362, %p58;
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selp.f32 %f368, %f366, %f364, %p58;
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add.f32 %f369, %f367, 0fBF800000;
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add.f32 %f358, %f367, 0f3F800000;
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// inline asm
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rcp.approx.ftz.f32 %f357,%f358;
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// inline asm
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add.f32 %f370, %f369, %f369;
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mul.f32 %f371, %f357, %f370;
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mul.f32 %f372, %f371, %f371;
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mov.f32 %f373, 0f3C4CAF63;
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mov.f32 %f374, 0f3B18F0FE;
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fma.rn.f32 %f375, %f374, %f372, %f373;
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mov.f32 %f376, 0f3DAAAABD;
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fma.rn.f32 %f377, %f375, %f372, %f376;
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mul.rn.f32 %f378, %f377, %f372;
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mul.rn.f32 %f379, %f378, %f371;
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sub.f32 %f380, %f369, %f371;
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neg.f32 %f381, %f371;
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add.f32 %f382, %f380, %f380;
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fma.rn.f32 %f383, %f381, %f369, %f382;
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mul.rn.f32 %f384, %f357, %f383;
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add.f32 %f385, %f379, %f371;
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sub.f32 %f386, %f371, %f385;
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add.f32 %f387, %f379, %f386;
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add.f32 %f388, %f384, %f387;
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add.f32 %f389, %f385, %f388;
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sub.f32 %f390, %f385, %f389;
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add.f32 %f391, %f388, %f390;
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mov.f32 %f392, 0f3F317200;
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mul.rn.f32 %f393, %f368, %f392;
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mov.f32 %f394, 0f35BFBE8E;
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mul.rn.f32 %f395, %f368, %f394;
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add.f32 %f396, %f393, %f389;
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sub.f32 %f397, %f393, %f396;
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add.f32 %f398, %f389, %f397;
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add.f32 %f399, %f391, %f398;
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add.f32 %f400, %f395, %f399;
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add.f32 %f401, %f396, %f400;
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sub.f32 %f402, %f396, %f401;
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add.f32 %f403, %f400, %f402;
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mov.f32 %f404, 0f400CCCCD;
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mul.rn.f32 %f405, %f404, %f401;
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neg.f32 %f406, %f405;
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fma.rn.f32 %f407, %f404, %f401, %f406;
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fma.rn.f32 %f408, %f404, %f403, %f407;
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mov.f32 %f409, 0f00000000;
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fma.rn.f32 %f410, %f409, %f401, %f408;
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add.rn.f32 %f411, %f405, %f410;
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neg.f32 %f412, %f411;
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add.rn.f32 %f413, %f405, %f412;
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add.rn.f32 %f414, %f413, %f410;
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mov.b32 %r57, %f411;
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setp.eq.s32 %p59, %r57, 1118925336;
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add.s32 %r58, %r57, -1;
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mov.b32 %f415, %r58;
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add.f32 %f416, %f414, 0f37000000;
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selp.f32 %f417, %f415, %f411, %p59;
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selp.f32 %f53, %f416, %f414, %p59;
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mul.f32 %f418, %f417, 0f3FB8AA3B;
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cvt.rzi.f32.f32 %f419, %f418;
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mov.f32 %f420, 0fBF317200;
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fma.rn.f32 %f421, %f419, %f420, %f417;
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mov.f32 %f422, 0fB5BFBE8E;
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fma.rn.f32 %f423, %f419, %f422, %f421;
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mul.f32 %f424, %f423, 0f3FB8AA3B;
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ex2.approx.ftz.f32 %f425, %f424;
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add.f32 %f426, %f419, 0f00000000;
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ex2.approx.f32 %f427, %f426;
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mul.f32 %f428, %f425, %f427;
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setp.lt.f32 %p60, %f417, 0fC2D20000;
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selp.f32 %f429, 0f00000000, %f428, %p60;
|
|
setp.gt.f32 %p61, %f417, 0f42D20000;
|
|
selp.f32 %f657, 0f7F800000, %f429, %p61;
|
|
setp.eq.f32 %p62, %f657, 0f7F800000;
|
|
@%p62 bra BB0_37;
|
|
|
|
fma.rn.f32 %f657, %f657, %f53, %f657;
|
|
|
|
BB0_37:
|
|
setp.lt.f32 %p63, %f2, 0f00000000;
|
|
setp.eq.f32 %p64, %f4, 0f3F800000;
|
|
and.pred %p4, %p63, %p64;
|
|
mov.b32 %r59, %f657;
|
|
xor.b32 %r60, %r59, -2147483648;
|
|
mov.b32 %f430, %r60;
|
|
selp.f32 %f659, %f430, %f657, %p4;
|
|
setp.eq.f32 %p65, %f2, 0f00000000;
|
|
@%p65 bra BB0_40;
|
|
bra.uni BB0_38;
|
|
|
|
BB0_40:
|
|
add.f32 %f433, %f2, %f2;
|
|
selp.f32 %f659, %f433, 0f00000000, %p64;
|
|
bra.uni BB0_41;
|
|
|
|
BB0_4:
|
|
setp.geu.f32 %p18, %f8, 0f00000000;
|
|
@%p18 bra BB0_7;
|
|
|
|
mov.f32 %f630, 0f400CCCCD;
|
|
cvt.rzi.f32.f32 %f184, %f630;
|
|
setp.neu.f32 %p19, %f184, 0f400CCCCD;
|
|
selp.f32 %f650, 0f7FFFFFFF, %f650, %p19;
|
|
|
|
BB0_7:
|
|
abs.f32 %f604, %f8;
|
|
add.f32 %f186, %f604, 0f400CCCCD;
|
|
mov.b32 %r34, %f186;
|
|
setp.lt.s32 %p21, %r34, 2139095040;
|
|
@%p21 bra BB0_12;
|
|
|
|
abs.f32 %f628, %f8;
|
|
setp.gtu.f32 %p22, %f628, 0f7F800000;
|
|
@%p22 bra BB0_11;
|
|
bra.uni BB0_9;
|
|
|
|
BB0_11:
|
|
add.f32 %f650, %f8, 0f400CCCCD;
|
|
bra.uni BB0_12;
|
|
|
|
BB0_9:
|
|
abs.f32 %f629, %f8;
|
|
setp.neu.f32 %p23, %f629, 0f7F800000;
|
|
@%p23 bra BB0_12;
|
|
|
|
selp.f32 %f650, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
BB0_12:
|
|
mov.f32 %f614, 0fB5BFBE8E;
|
|
mov.f32 %f613, 0fBF317200;
|
|
mov.f32 %f612, 0f00000000;
|
|
mov.f32 %f611, 0f35BFBE8E;
|
|
mov.f32 %f610, 0f3F317200;
|
|
mov.f32 %f609, 0f3DAAAABD;
|
|
mov.f32 %f608, 0f3C4CAF63;
|
|
mov.f32 %f607, 0f3B18F0FE;
|
|
mov.f32 %f606, 0f3F800000;
|
|
mov.f32 %f605, 0f400CCCCD;
|
|
setp.eq.f32 %p24, %f8, 0f3F800000;
|
|
selp.f32 %f189, 0f3F800000, %f650, %p24;
|
|
cvt.sat.f32.f32 %f21, %f189;
|
|
sub.f32 %f22, %f606, %f97;
|
|
abs.f32 %f23, %f22;
|
|
setp.lt.f32 %p25, %f23, 0f00800000;
|
|
mul.f32 %f191, %f23, 0f4B800000;
|
|
selp.f32 %f192, 0fC3170000, 0fC2FE0000, %p25;
|
|
selp.f32 %f193, %f191, %f23, %p25;
|
|
mov.b32 %r35, %f193;
|
|
and.b32 %r36, %r35, 8388607;
|
|
or.b32 %r37, %r36, 1065353216;
|
|
mov.b32 %f194, %r37;
|
|
shr.u32 %r38, %r35, 23;
|
|
cvt.rn.f32.u32 %f195, %r38;
|
|
add.f32 %f196, %f192, %f195;
|
|
setp.gt.f32 %p26, %f194, 0f3FB504F3;
|
|
mul.f32 %f197, %f194, 0f3F000000;
|
|
add.f32 %f198, %f196, 0f3F800000;
|
|
selp.f32 %f199, %f197, %f194, %p26;
|
|
selp.f32 %f200, %f198, %f196, %p26;
|
|
add.f32 %f201, %f199, 0fBF800000;
|
|
add.f32 %f188, %f199, 0f3F800000;
|
|
// inline asm
|
|
rcp.approx.ftz.f32 %f187,%f188;
|
|
// inline asm
|
|
add.f32 %f202, %f201, %f201;
|
|
mul.f32 %f203, %f187, %f202;
|
|
mul.f32 %f204, %f203, %f203;
|
|
fma.rn.f32 %f207, %f607, %f204, %f608;
|
|
fma.rn.f32 %f209, %f207, %f204, %f609;
|
|
mul.rn.f32 %f210, %f209, %f204;
|
|
mul.rn.f32 %f211, %f210, %f203;
|
|
sub.f32 %f212, %f201, %f203;
|
|
neg.f32 %f213, %f203;
|
|
add.f32 %f214, %f212, %f212;
|
|
fma.rn.f32 %f215, %f213, %f201, %f214;
|
|
mul.rn.f32 %f216, %f187, %f215;
|
|
add.f32 %f217, %f211, %f203;
|
|
sub.f32 %f218, %f203, %f217;
|
|
add.f32 %f219, %f211, %f218;
|
|
add.f32 %f220, %f216, %f219;
|
|
add.f32 %f221, %f217, %f220;
|
|
sub.f32 %f222, %f217, %f221;
|
|
add.f32 %f223, %f220, %f222;
|
|
mul.rn.f32 %f225, %f200, %f610;
|
|
mul.rn.f32 %f227, %f200, %f611;
|
|
add.f32 %f228, %f225, %f221;
|
|
sub.f32 %f229, %f225, %f228;
|
|
add.f32 %f230, %f221, %f229;
|
|
add.f32 %f231, %f223, %f230;
|
|
add.f32 %f232, %f227, %f231;
|
|
add.f32 %f233, %f228, %f232;
|
|
sub.f32 %f234, %f228, %f233;
|
|
add.f32 %f235, %f232, %f234;
|
|
mul.rn.f32 %f237, %f605, %f233;
|
|
neg.f32 %f238, %f237;
|
|
fma.rn.f32 %f239, %f605, %f233, %f238;
|
|
fma.rn.f32 %f240, %f605, %f235, %f239;
|
|
fma.rn.f32 %f242, %f612, %f233, %f240;
|
|
add.rn.f32 %f243, %f237, %f242;
|
|
neg.f32 %f244, %f243;
|
|
add.rn.f32 %f245, %f237, %f244;
|
|
add.rn.f32 %f246, %f245, %f242;
|
|
mov.b32 %r39, %f243;
|
|
setp.eq.s32 %p27, %r39, 1118925336;
|
|
add.s32 %r40, %r39, -1;
|
|
mov.b32 %f247, %r40;
|
|
add.f32 %f248, %f246, 0f37000000;
|
|
selp.f32 %f249, %f247, %f243, %p27;
|
|
selp.f32 %f24, %f248, %f246, %p27;
|
|
mul.f32 %f250, %f249, 0f3FB8AA3B;
|
|
cvt.rzi.f32.f32 %f251, %f250;
|
|
fma.rn.f32 %f253, %f251, %f613, %f249;
|
|
fma.rn.f32 %f255, %f251, %f614, %f253;
|
|
mul.f32 %f256, %f255, 0f3FB8AA3B;
|
|
ex2.approx.ftz.f32 %f257, %f256;
|
|
add.f32 %f258, %f251, 0f00000000;
|
|
ex2.approx.f32 %f259, %f258;
|
|
mul.f32 %f260, %f257, %f259;
|
|
setp.lt.f32 %p28, %f249, 0fC2D20000;
|
|
selp.f32 %f261, 0f00000000, %f260, %p28;
|
|
setp.gt.f32 %p29, %f249, 0f42D20000;
|
|
selp.f32 %f651, 0f7F800000, %f261, %p29;
|
|
setp.eq.f32 %p30, %f651, 0f7F800000;
|
|
@%p30 bra BB0_14;
|
|
|
|
fma.rn.f32 %f651, %f651, %f24, %f651;
|
|
|
|
BB0_14:
|
|
setp.lt.f32 %p31, %f22, 0f00000000;
|
|
and.pred %p2, %p31, %p16;
|
|
mov.b32 %r41, %f651;
|
|
xor.b32 %r42, %r41, -2147483648;
|
|
mov.b32 %f262, %r42;
|
|
selp.f32 %f653, %f262, %f651, %p2;
|
|
setp.eq.f32 %p33, %f22, 0f00000000;
|
|
@%p33 bra BB0_17;
|
|
bra.uni BB0_15;
|
|
|
|
BB0_17:
|
|
add.f32 %f265, %f22, %f22;
|
|
selp.f32 %f653, %f265, 0f00000000, %p16;
|
|
bra.uni BB0_18;
|
|
|
|
BB0_15:
|
|
setp.geu.f32 %p34, %f22, 0f00000000;
|
|
@%p34 bra BB0_18;
|
|
|
|
mov.f32 %f627, 0f400CCCCD;
|
|
cvt.rzi.f32.f32 %f264, %f627;
|
|
setp.neu.f32 %p35, %f264, 0f400CCCCD;
|
|
selp.f32 %f653, 0f7FFFFFFF, %f653, %p35;
|
|
|
|
BB0_18:
|
|
add.f32 %f266, %f23, 0f400CCCCD;
|
|
mov.b32 %r43, %f266;
|
|
setp.lt.s32 %p37, %r43, 2139095040;
|
|
@%p37 bra BB0_23;
|
|
|
|
setp.gtu.f32 %p38, %f23, 0f7F800000;
|
|
@%p38 bra BB0_22;
|
|
bra.uni BB0_20;
|
|
|
|
BB0_22:
|
|
add.f32 %f653, %f22, 0f400CCCCD;
|
|
bra.uni BB0_23;
|
|
|
|
BB0_20:
|
|
setp.neu.f32 %p39, %f23, 0f7F800000;
|
|
@%p39 bra BB0_23;
|
|
|
|
selp.f32 %f653, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
BB0_23:
|
|
mov.f32 %f624, 0fB5BFBE8E;
|
|
mov.f32 %f623, 0fBF317200;
|
|
mov.f32 %f622, 0f00000000;
|
|
mov.f32 %f621, 0f35BFBE8E;
|
|
mov.f32 %f620, 0f3F317200;
|
|
mov.f32 %f619, 0f3DAAAABD;
|
|
mov.f32 %f618, 0f3C4CAF63;
|
|
mov.f32 %f617, 0f3B18F0FE;
|
|
mov.f32 %f616, 0f3F800000;
|
|
mov.f32 %f615, 0f400CCCCD;
|
|
setp.eq.f32 %p40, %f22, 0f3F800000;
|
|
selp.f32 %f269, 0f3F800000, %f653, %p40;
|
|
cvt.sat.f32.f32 %f35, %f269;
|
|
sub.f32 %f36, %f616, %f3;
|
|
abs.f32 %f37, %f36;
|
|
setp.lt.f32 %p41, %f37, 0f00800000;
|
|
mul.f32 %f271, %f37, 0f4B800000;
|
|
selp.f32 %f272, 0fC3170000, 0fC2FE0000, %p41;
|
|
selp.f32 %f273, %f271, %f37, %p41;
|
|
mov.b32 %r44, %f273;
|
|
and.b32 %r45, %r44, 8388607;
|
|
or.b32 %r46, %r45, 1065353216;
|
|
mov.b32 %f274, %r46;
|
|
shr.u32 %r47, %r44, 23;
|
|
cvt.rn.f32.u32 %f275, %r47;
|
|
add.f32 %f276, %f272, %f275;
|
|
setp.gt.f32 %p42, %f274, 0f3FB504F3;
|
|
mul.f32 %f277, %f274, 0f3F000000;
|
|
add.f32 %f278, %f276, 0f3F800000;
|
|
selp.f32 %f279, %f277, %f274, %p42;
|
|
selp.f32 %f280, %f278, %f276, %p42;
|
|
add.f32 %f281, %f279, 0fBF800000;
|
|
add.f32 %f268, %f279, 0f3F800000;
|
|
// inline asm
|
|
rcp.approx.ftz.f32 %f267,%f268;
|
|
// inline asm
|
|
add.f32 %f282, %f281, %f281;
|
|
mul.f32 %f283, %f267, %f282;
|
|
mul.f32 %f284, %f283, %f283;
|
|
fma.rn.f32 %f287, %f617, %f284, %f618;
|
|
fma.rn.f32 %f289, %f287, %f284, %f619;
|
|
mul.rn.f32 %f290, %f289, %f284;
|
|
mul.rn.f32 %f291, %f290, %f283;
|
|
sub.f32 %f292, %f281, %f283;
|
|
neg.f32 %f293, %f283;
|
|
add.f32 %f294, %f292, %f292;
|
|
fma.rn.f32 %f295, %f293, %f281, %f294;
|
|
mul.rn.f32 %f296, %f267, %f295;
|
|
add.f32 %f297, %f291, %f283;
|
|
sub.f32 %f298, %f283, %f297;
|
|
add.f32 %f299, %f291, %f298;
|
|
add.f32 %f300, %f296, %f299;
|
|
add.f32 %f301, %f297, %f300;
|
|
sub.f32 %f302, %f297, %f301;
|
|
add.f32 %f303, %f300, %f302;
|
|
mul.rn.f32 %f305, %f280, %f620;
|
|
mul.rn.f32 %f307, %f280, %f621;
|
|
add.f32 %f308, %f305, %f301;
|
|
sub.f32 %f309, %f305, %f308;
|
|
add.f32 %f310, %f301, %f309;
|
|
add.f32 %f311, %f303, %f310;
|
|
add.f32 %f312, %f307, %f311;
|
|
add.f32 %f313, %f308, %f312;
|
|
sub.f32 %f314, %f308, %f313;
|
|
add.f32 %f315, %f312, %f314;
|
|
mul.rn.f32 %f317, %f615, %f313;
|
|
neg.f32 %f318, %f317;
|
|
fma.rn.f32 %f319, %f615, %f313, %f318;
|
|
fma.rn.f32 %f320, %f615, %f315, %f319;
|
|
fma.rn.f32 %f322, %f622, %f313, %f320;
|
|
add.rn.f32 %f323, %f317, %f322;
|
|
neg.f32 %f324, %f323;
|
|
add.rn.f32 %f325, %f317, %f324;
|
|
add.rn.f32 %f326, %f325, %f322;
|
|
mov.b32 %r48, %f323;
|
|
setp.eq.s32 %p43, %r48, 1118925336;
|
|
add.s32 %r49, %r48, -1;
|
|
mov.b32 %f327, %r49;
|
|
add.f32 %f328, %f326, 0f37000000;
|
|
selp.f32 %f329, %f327, %f323, %p43;
|
|
selp.f32 %f38, %f328, %f326, %p43;
|
|
mul.f32 %f330, %f329, 0f3FB8AA3B;
|
|
cvt.rzi.f32.f32 %f331, %f330;
|
|
fma.rn.f32 %f333, %f331, %f623, %f329;
|
|
fma.rn.f32 %f335, %f331, %f624, %f333;
|
|
mul.f32 %f336, %f335, 0f3FB8AA3B;
|
|
ex2.approx.ftz.f32 %f337, %f336;
|
|
add.f32 %f338, %f331, 0f00000000;
|
|
ex2.approx.f32 %f339, %f338;
|
|
mul.f32 %f340, %f337, %f339;
|
|
setp.lt.f32 %p44, %f329, 0fC2D20000;
|
|
selp.f32 %f341, 0f00000000, %f340, %p44;
|
|
setp.gt.f32 %p45, %f329, 0f42D20000;
|
|
selp.f32 %f654, 0f7F800000, %f341, %p45;
|
|
setp.eq.f32 %p46, %f654, 0f7F800000;
|
|
@%p46 bra BB0_25;
|
|
|
|
fma.rn.f32 %f654, %f654, %f38, %f654;
|
|
|
|
BB0_25:
|
|
setp.lt.f32 %p47, %f36, 0f00000000;
|
|
and.pred %p3, %p47, %p16;
|
|
mov.b32 %r50, %f654;
|
|
xor.b32 %r51, %r50, -2147483648;
|
|
mov.b32 %f342, %r51;
|
|
selp.f32 %f656, %f342, %f654, %p3;
|
|
setp.eq.f32 %p49, %f36, 0f00000000;
|
|
@%p49 bra BB0_28;
|
|
bra.uni BB0_26;
|
|
|
|
BB0_28:
|
|
add.f32 %f345, %f36, %f36;
|
|
selp.f32 %f656, %f345, 0f00000000, %p16;
|
|
bra.uni BB0_29;
|
|
|
|
BB0_26:
|
|
setp.geu.f32 %p50, %f36, 0f00000000;
|
|
@%p50 bra BB0_29;
|
|
|
|
mov.f32 %f626, 0f400CCCCD;
|
|
cvt.rzi.f32.f32 %f344, %f626;
|
|
setp.neu.f32 %p51, %f344, 0f400CCCCD;
|
|
selp.f32 %f656, 0f7FFFFFFF, %f656, %p51;
|
|
|
|
BB0_29:
|
|
abs.f32 %f631, %f36;
|
|
add.f32 %f346, %f631, 0f400CCCCD;
|
|
mov.b32 %r52, %f346;
|
|
setp.lt.s32 %p53, %r52, 2139095040;
|
|
@%p53 bra BB0_34;
|
|
|
|
abs.f32 %f632, %f36;
|
|
setp.gtu.f32 %p54, %f632, 0f7F800000;
|
|
@%p54 bra BB0_33;
|
|
bra.uni BB0_31;
|
|
|
|
BB0_33:
|
|
add.f32 %f656, %f36, 0f400CCCCD;
|
|
bra.uni BB0_34;
|
|
|
|
BB0_31:
|
|
abs.f32 %f633, %f36;
|
|
setp.neu.f32 %p55, %f633, 0f7F800000;
|
|
@%p55 bra BB0_34;
|
|
|
|
selp.f32 %f656, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
BB0_34:
|
|
mov.f32 %f625, 0f3F800000;
|
|
setp.eq.f32 %p56, %f36, 0f3F800000;
|
|
selp.f32 %f347, 0f3F800000, %f656, %p56;
|
|
cvt.sat.f32.f32 %f348, %f347;
|
|
max.f32 %f349, %f21, %f35;
|
|
max.f32 %f350, %f349, %f348;
|
|
sub.f32 %f352, %f625, %f350;
|
|
rcp.rn.f32 %f353, %f352;
|
|
mul.f32 %f354, %f21, %f353;
|
|
mul.f32 %f355, %f35, %f353;
|
|
mul.f32 %f356, %f348, %f353;
|
|
min.f32 %f666, %f354, %f105;
|
|
min.f32 %f667, %f355, %f106;
|
|
min.f32 %f668, %f356, %f107;
|
|
bra.uni BB0_69;
|
|
|
|
BB0_38:
|
|
setp.geu.f32 %p66, %f2, 0f00000000;
|
|
@%p66 bra BB0_41;
|
|
|
|
cvt.rzi.f32.f32 %f432, %f404;
|
|
setp.neu.f32 %p67, %f432, 0f400CCCCD;
|
|
selp.f32 %f659, 0f7FFFFFFF, %f659, %p67;
|
|
|
|
BB0_41:
|
|
add.f32 %f434, %f52, 0f400CCCCD;
|
|
mov.b32 %r61, %f434;
|
|
setp.lt.s32 %p69, %r61, 2139095040;
|
|
@%p69 bra BB0_46;
|
|
|
|
setp.gtu.f32 %p70, %f52, 0f7F800000;
|
|
@%p70 bra BB0_45;
|
|
bra.uni BB0_43;
|
|
|
|
BB0_45:
|
|
add.f32 %f659, %f2, 0f400CCCCD;
|
|
bra.uni BB0_46;
|
|
|
|
BB0_43:
|
|
setp.neu.f32 %p71, %f52, 0f7F800000;
|
|
@%p71 bra BB0_46;
|
|
|
|
selp.f32 %f659, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
BB0_46:
|
|
mov.f32 %f640, 0fBF317200;
|
|
mov.f32 %f639, 0f00000000;
|
|
mov.f32 %f638, 0f35BFBE8E;
|
|
mov.f32 %f637, 0f3F317200;
|
|
mov.f32 %f636, 0f3DAAAABD;
|
|
mov.f32 %f635, 0f3C4CAF63;
|
|
mov.f32 %f634, 0f3B18F0FE;
|
|
setp.eq.f32 %p72, %f2, 0f3F800000;
|
|
selp.f32 %f437, 0f3F800000, %f659, %p72;
|
|
cvt.sat.f32.f32 %f64, %f437;
|
|
abs.f32 %f65, %f97;
|
|
setp.lt.f32 %p73, %f65, 0f00800000;
|
|
mul.f32 %f438, %f65, 0f4B800000;
|
|
selp.f32 %f439, 0fC3170000, 0fC2FE0000, %p73;
|
|
selp.f32 %f440, %f438, %f65, %p73;
|
|
mov.b32 %r62, %f440;
|
|
and.b32 %r63, %r62, 8388607;
|
|
or.b32 %r64, %r63, 1065353216;
|
|
mov.b32 %f441, %r64;
|
|
shr.u32 %r65, %r62, 23;
|
|
cvt.rn.f32.u32 %f442, %r65;
|
|
add.f32 %f443, %f439, %f442;
|
|
setp.gt.f32 %p74, %f441, 0f3FB504F3;
|
|
mul.f32 %f444, %f441, 0f3F000000;
|
|
add.f32 %f445, %f443, 0f3F800000;
|
|
selp.f32 %f446, %f444, %f441, %p74;
|
|
selp.f32 %f447, %f445, %f443, %p74;
|
|
add.f32 %f448, %f446, 0fBF800000;
|
|
add.f32 %f436, %f446, 0f3F800000;
|
|
// inline asm
|
|
rcp.approx.ftz.f32 %f435,%f436;
|
|
// inline asm
|
|
add.f32 %f449, %f448, %f448;
|
|
mul.f32 %f450, %f435, %f449;
|
|
mul.f32 %f451, %f450, %f450;
|
|
fma.rn.f32 %f454, %f634, %f451, %f635;
|
|
fma.rn.f32 %f456, %f454, %f451, %f636;
|
|
mul.rn.f32 %f457, %f456, %f451;
|
|
mul.rn.f32 %f458, %f457, %f450;
|
|
sub.f32 %f459, %f448, %f450;
|
|
neg.f32 %f460, %f450;
|
|
add.f32 %f461, %f459, %f459;
|
|
fma.rn.f32 %f462, %f460, %f448, %f461;
|
|
mul.rn.f32 %f463, %f435, %f462;
|
|
add.f32 %f464, %f458, %f450;
|
|
sub.f32 %f465, %f450, %f464;
|
|
add.f32 %f466, %f458, %f465;
|
|
add.f32 %f467, %f463, %f466;
|
|
add.f32 %f468, %f464, %f467;
|
|
sub.f32 %f469, %f464, %f468;
|
|
add.f32 %f470, %f467, %f469;
|
|
mul.rn.f32 %f472, %f447, %f637;
|
|
mul.rn.f32 %f474, %f447, %f638;
|
|
add.f32 %f475, %f472, %f468;
|
|
sub.f32 %f476, %f472, %f475;
|
|
add.f32 %f477, %f468, %f476;
|
|
add.f32 %f478, %f470, %f477;
|
|
add.f32 %f479, %f474, %f478;
|
|
add.f32 %f480, %f475, %f479;
|
|
sub.f32 %f481, %f475, %f480;
|
|
add.f32 %f482, %f479, %f481;
|
|
mul.rn.f32 %f484, %f404, %f480;
|
|
neg.f32 %f485, %f484;
|
|
fma.rn.f32 %f486, %f404, %f480, %f485;
|
|
fma.rn.f32 %f487, %f404, %f482, %f486;
|
|
fma.rn.f32 %f489, %f639, %f480, %f487;
|
|
add.rn.f32 %f490, %f484, %f489;
|
|
neg.f32 %f491, %f490;
|
|
add.rn.f32 %f492, %f484, %f491;
|
|
add.rn.f32 %f493, %f492, %f489;
|
|
mov.b32 %r66, %f490;
|
|
setp.eq.s32 %p75, %r66, 1118925336;
|
|
add.s32 %r67, %r66, -1;
|
|
mov.b32 %f494, %r67;
|
|
add.f32 %f495, %f493, 0f37000000;
|
|
selp.f32 %f496, %f494, %f490, %p75;
|
|
selp.f32 %f66, %f495, %f493, %p75;
|
|
mul.f32 %f497, %f496, 0f3FB8AA3B;
|
|
cvt.rzi.f32.f32 %f498, %f497;
|
|
fma.rn.f32 %f500, %f498, %f640, %f496;
|
|
fma.rn.f32 %f502, %f498, %f422, %f500;
|
|
mul.f32 %f503, %f502, 0f3FB8AA3B;
|
|
ex2.approx.ftz.f32 %f504, %f503;
|
|
add.f32 %f505, %f498, 0f00000000;
|
|
ex2.approx.f32 %f506, %f505;
|
|
mul.f32 %f507, %f504, %f506;
|
|
setp.lt.f32 %p76, %f496, 0fC2D20000;
|
|
selp.f32 %f508, 0f00000000, %f507, %p76;
|
|
setp.gt.f32 %p77, %f496, 0f42D20000;
|
|
selp.f32 %f660, 0f7F800000, %f508, %p77;
|
|
setp.eq.f32 %p78, %f660, 0f7F800000;
|
|
@%p78 bra BB0_48;
|
|
|
|
fma.rn.f32 %f660, %f660, %f66, %f660;
|
|
|
|
BB0_48:
|
|
setp.lt.f32 %p79, %f97, 0f00000000;
|
|
and.pred %p5, %p79, %p64;
|
|
mov.b32 %r68, %f660;
|
|
xor.b32 %r69, %r68, -2147483648;
|
|
mov.b32 %f509, %r69;
|
|
selp.f32 %f662, %f509, %f660, %p5;
|
|
setp.eq.f32 %p81, %f97, 0f00000000;
|
|
@%p81 bra BB0_51;
|
|
bra.uni BB0_49;
|
|
|
|
BB0_51:
|
|
add.f32 %f512, %f97, %f97;
|
|
selp.f32 %f662, %f512, 0f00000000, %p64;
|
|
bra.uni BB0_52;
|
|
|
|
BB0_49:
|
|
setp.geu.f32 %p82, %f97, 0f00000000;
|
|
@%p82 bra BB0_52;
|
|
|
|
cvt.rzi.f32.f32 %f511, %f404;
|
|
setp.neu.f32 %p83, %f511, 0f400CCCCD;
|
|
selp.f32 %f662, 0f7FFFFFFF, %f662, %p83;
|
|
|
|
BB0_52:
|
|
add.f32 %f513, %f65, 0f400CCCCD;
|
|
mov.b32 %r70, %f513;
|
|
setp.lt.s32 %p85, %r70, 2139095040;
|
|
@%p85 bra BB0_57;
|
|
|
|
setp.gtu.f32 %p86, %f65, 0f7F800000;
|
|
@%p86 bra BB0_56;
|
|
bra.uni BB0_54;
|
|
|
|
BB0_56:
|
|
add.f32 %f662, %f97, 0f400CCCCD;
|
|
bra.uni BB0_57;
|
|
|
|
BB0_54:
|
|
setp.neu.f32 %p87, %f65, 0f7F800000;
|
|
@%p87 bra BB0_57;
|
|
|
|
selp.f32 %f662, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
BB0_57:
|
|
mov.f32 %f647, 0fBF317200;
|
|
mov.f32 %f646, 0f00000000;
|
|
mov.f32 %f645, 0f35BFBE8E;
|
|
mov.f32 %f644, 0f3F317200;
|
|
mov.f32 %f643, 0f3DAAAABD;
|
|
mov.f32 %f642, 0f3C4CAF63;
|
|
mov.f32 %f641, 0f3B18F0FE;
|
|
setp.eq.f32 %p88, %f97, 0f3F800000;
|
|
selp.f32 %f516, 0f3F800000, %f662, %p88;
|
|
cvt.sat.f32.f32 %f77, %f516;
|
|
abs.f32 %f78, %f3;
|
|
setp.lt.f32 %p89, %f78, 0f00800000;
|
|
mul.f32 %f517, %f78, 0f4B800000;
|
|
selp.f32 %f518, 0fC3170000, 0fC2FE0000, %p89;
|
|
selp.f32 %f519, %f517, %f78, %p89;
|
|
mov.b32 %r71, %f519;
|
|
and.b32 %r72, %r71, 8388607;
|
|
or.b32 %r73, %r72, 1065353216;
|
|
mov.b32 %f520, %r73;
|
|
shr.u32 %r74, %r71, 23;
|
|
cvt.rn.f32.u32 %f521, %r74;
|
|
add.f32 %f522, %f518, %f521;
|
|
setp.gt.f32 %p90, %f520, 0f3FB504F3;
|
|
mul.f32 %f523, %f520, 0f3F000000;
|
|
add.f32 %f524, %f522, 0f3F800000;
|
|
selp.f32 %f525, %f523, %f520, %p90;
|
|
selp.f32 %f526, %f524, %f522, %p90;
|
|
add.f32 %f527, %f525, 0fBF800000;
|
|
add.f32 %f515, %f525, 0f3F800000;
|
|
// inline asm
|
|
rcp.approx.ftz.f32 %f514,%f515;
|
|
// inline asm
|
|
add.f32 %f528, %f527, %f527;
|
|
mul.f32 %f529, %f514, %f528;
|
|
mul.f32 %f530, %f529, %f529;
|
|
fma.rn.f32 %f533, %f641, %f530, %f642;
|
|
fma.rn.f32 %f535, %f533, %f530, %f643;
|
|
mul.rn.f32 %f536, %f535, %f530;
|
|
mul.rn.f32 %f537, %f536, %f529;
|
|
sub.f32 %f538, %f527, %f529;
|
|
neg.f32 %f539, %f529;
|
|
add.f32 %f540, %f538, %f538;
|
|
fma.rn.f32 %f541, %f539, %f527, %f540;
|
|
mul.rn.f32 %f542, %f514, %f541;
|
|
add.f32 %f543, %f537, %f529;
|
|
sub.f32 %f544, %f529, %f543;
|
|
add.f32 %f545, %f537, %f544;
|
|
add.f32 %f546, %f542, %f545;
|
|
add.f32 %f547, %f543, %f546;
|
|
sub.f32 %f548, %f543, %f547;
|
|
add.f32 %f549, %f546, %f548;
|
|
mul.rn.f32 %f551, %f526, %f644;
|
|
mul.rn.f32 %f553, %f526, %f645;
|
|
add.f32 %f554, %f551, %f547;
|
|
sub.f32 %f555, %f551, %f554;
|
|
add.f32 %f556, %f547, %f555;
|
|
add.f32 %f557, %f549, %f556;
|
|
add.f32 %f558, %f553, %f557;
|
|
add.f32 %f559, %f554, %f558;
|
|
sub.f32 %f560, %f554, %f559;
|
|
add.f32 %f561, %f558, %f560;
|
|
mul.rn.f32 %f563, %f404, %f559;
|
|
neg.f32 %f564, %f563;
|
|
fma.rn.f32 %f565, %f404, %f559, %f564;
|
|
fma.rn.f32 %f566, %f404, %f561, %f565;
|
|
fma.rn.f32 %f568, %f646, %f559, %f566;
|
|
add.rn.f32 %f569, %f563, %f568;
|
|
neg.f32 %f570, %f569;
|
|
add.rn.f32 %f571, %f563, %f570;
|
|
add.rn.f32 %f572, %f571, %f568;
|
|
mov.b32 %r75, %f569;
|
|
setp.eq.s32 %p91, %r75, 1118925336;
|
|
add.s32 %r76, %r75, -1;
|
|
mov.b32 %f573, %r76;
|
|
add.f32 %f574, %f572, 0f37000000;
|
|
selp.f32 %f575, %f573, %f569, %p91;
|
|
selp.f32 %f79, %f574, %f572, %p91;
|
|
mul.f32 %f576, %f575, 0f3FB8AA3B;
|
|
cvt.rzi.f32.f32 %f577, %f576;
|
|
fma.rn.f32 %f579, %f577, %f647, %f575;
|
|
fma.rn.f32 %f581, %f577, %f422, %f579;
|
|
mul.f32 %f582, %f581, 0f3FB8AA3B;
|
|
ex2.approx.ftz.f32 %f583, %f582;
|
|
add.f32 %f584, %f577, 0f00000000;
|
|
ex2.approx.f32 %f585, %f584;
|
|
mul.f32 %f586, %f583, %f585;
|
|
setp.lt.f32 %p92, %f575, 0fC2D20000;
|
|
selp.f32 %f587, 0f00000000, %f586, %p92;
|
|
setp.gt.f32 %p93, %f575, 0f42D20000;
|
|
selp.f32 %f663, 0f7F800000, %f587, %p93;
|
|
setp.eq.f32 %p94, %f663, 0f7F800000;
|
|
@%p94 bra BB0_59;
|
|
|
|
fma.rn.f32 %f663, %f663, %f79, %f663;
|
|
|
|
BB0_59:
|
|
setp.lt.f32 %p95, %f3, 0f00000000;
|
|
and.pred %p6, %p95, %p64;
|
|
mov.b32 %r77, %f663;
|
|
xor.b32 %r78, %r77, -2147483648;
|
|
mov.b32 %f588, %r78;
|
|
selp.f32 %f665, %f588, %f663, %p6;
|
|
setp.eq.f32 %p97, %f3, 0f00000000;
|
|
@%p97 bra BB0_62;
|
|
bra.uni BB0_60;
|
|
|
|
BB0_62:
|
|
add.f32 %f591, %f3, %f3;
|
|
selp.f32 %f665, %f591, 0f00000000, %p64;
|
|
bra.uni BB0_63;
|
|
|
|
BB0_60:
|
|
setp.geu.f32 %p98, %f3, 0f00000000;
|
|
@%p98 bra BB0_63;
|
|
|
|
cvt.rzi.f32.f32 %f590, %f404;
|
|
setp.neu.f32 %p99, %f590, 0f400CCCCD;
|
|
selp.f32 %f665, 0f7FFFFFFF, %f665, %p99;
|
|
|
|
BB0_63:
|
|
add.f32 %f592, %f78, 0f400CCCCD;
|
|
mov.b32 %r79, %f592;
|
|
setp.lt.s32 %p101, %r79, 2139095040;
|
|
@%p101 bra BB0_68;
|
|
|
|
setp.gtu.f32 %p102, %f78, 0f7F800000;
|
|
@%p102 bra BB0_67;
|
|
bra.uni BB0_65;
|
|
|
|
BB0_67:
|
|
add.f32 %f665, %f3, 0f400CCCCD;
|
|
bra.uni BB0_68;
|
|
|
|
BB0_65:
|
|
setp.neu.f32 %p103, %f78, 0f7F800000;
|
|
@%p103 bra BB0_68;
|
|
|
|
selp.f32 %f665, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
BB0_68:
|
|
setp.eq.f32 %p104, %f3, 0f3F800000;
|
|
selp.f32 %f593, 0f3F800000, %f665, %p104;
|
|
cvt.sat.f32.f32 %f594, %f593;
|
|
max.f32 %f595, %f64, %f77;
|
|
max.f32 %f596, %f595, %f594;
|
|
mov.f32 %f597, 0f3F800000;
|
|
sub.f32 %f598, %f597, %f596;
|
|
rcp.rn.f32 %f599, %f598;
|
|
mul.f32 %f666, %f64, %f599;
|
|
mul.f32 %f667, %f77, %f599;
|
|
mul.f32 %f668, %f594, %f599;
|
|
|
|
BB0_69:
|
|
mov.u64 %rd34, 0;
|
|
mov.u32 %r86, 2;
|
|
ld.global.v2.u32 {%r82, %r83}, [pixelID];
|
|
cvt.u64.u32 %rd29, %r82;
|
|
cvt.u64.u32 %rd30, %r83;
|
|
mov.u64 %rd33, image2;
|
|
cvta.global.u64 %rd28, %rd33;
|
|
mov.u32 %r81, 8;
|
|
// inline asm
|
|
call (%rd27), _rt_buffer_get_64, (%rd28, %r86, %r81, %rd29, %rd30, %rd34, %rd34);
|
|
// inline asm
|
|
mov.f32 %f603, 0f3F800000;
|
|
// inline asm
|
|
{ cvt.rn.f16.f32 %rs7, %f603;}
|
|
|
|
// inline asm
|
|
// inline asm
|
|
{ cvt.rn.f16.f32 %rs6, %f668;}
|
|
|
|
// inline asm
|
|
// inline asm
|
|
{ cvt.rn.f16.f32 %rs5, %f667;}
|
|
|
|
// inline asm
|
|
// inline asm
|
|
{ cvt.rn.f16.f32 %rs4, %f666;}
|
|
|
|
// inline asm
|
|
st.v4.u16 [%rd27], {%rs4, %rs5, %rs6, %rs7};
|
|
ret;
|
|
}
|
|
|
|
|