ArabDesert/Assets/Editor/x64/Bakery/denoisePrepareSH_OIDN.ptx

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//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-23083092
// Cuda compilation tools, release 9.1, V9.1.85
// Based on LLVM 3.4svn
//
.version 6.1
.target sm_30
.address_size 64
// .globl _Z6oxMainv
.global .align 8 .b8 pixelID[8];
.global .align 8 .b8 resolution[8];
.global .align 1 .b8 input_buffer[1];
.global .align 1 .b8 image[1];
.global .align 4 .u32 mode;
.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
.global .align 4 .b8 _ZN21rti_internal_typeinfo4modeE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
.global .align 4 .b8 _ZN21rti_internal_typename4modeE[4] = {105, 110, 116, 0};
.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
.global .align 4 .u32 _ZN21rti_internal_typeenum4modeE = 4919;
.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
.global .align 1 .b8 _ZN21rti_internal_semantic4modeE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
.global .align 1 .b8 _ZN23rti_internal_annotation4modeE[1];
.visible .entry _Z6oxMainv(
)
{
.reg .pred %p<2>;
.reg .b16 %rs<4>;
.reg .f32 %f<16>;
.reg .b32 %r<40>;
.reg .b64 %rd<48>;
ld.global.u32 %r1, [mode];
setp.gt.s32 %p1, %r1, 0;
ld.global.v2.u32 {%r2, %r3}, [pixelID];
cvt.u64.u32 %rd1, %r2;
cvt.u64.u32 %rd2, %r3;
@%p1 bra BB0_2;
bra.uni BB0_1;
BB0_2:
mov.u64 %rd40, input_buffer;
cvta.global.u64 %rd23, %rd40;
mov.u32 %r24, 2;
mov.u32 %r25, 12;
mov.u64 %rd39, 0;
// inline asm
call (%rd22), _rt_buffer_get_64, (%rd23, %r24, %r25, %rd1, %rd2, %rd39, %rd39);
// inline asm
ld.f32 %f13, [%rd22];
ld.global.v2.u32 {%r26, %r27}, [pixelID];
cvt.u64.u32 %rd30, %r26;
cvt.u64.u32 %rd31, %r27;
// inline asm
call (%rd28), _rt_buffer_get_64, (%rd23, %r24, %r25, %rd30, %rd31, %rd39, %rd39);
// inline asm
ld.f32 %f14, [%rd28+4];
ld.global.v2.u32 {%r30, %r31}, [pixelID];
cvt.u64.u32 %rd36, %r30;
cvt.u64.u32 %rd37, %r31;
// inline asm
call (%rd34), _rt_buffer_get_64, (%rd23, %r24, %r25, %rd36, %rd37, %rd39, %rd39);
// inline asm
ld.f32 %f15, [%rd34+8];
bra.uni BB0_3;
BB0_1:
mov.u64 %rd21, image;
cvta.global.u64 %rd4, %rd21;
mov.u32 %r10, 2;
mov.u32 %r11, 8;
mov.u64 %rd20, 0;
// inline asm
call (%rd3), _rt_buffer_get_64, (%rd4, %r10, %r11, %rd1, %rd2, %rd20, %rd20);
// inline asm
ld.u16 %rs1, [%rd3];
// inline asm
{ cvt.f32.f16 %f13, %rs1;}
// inline asm
ld.global.v2.u32 {%r12, %r13}, [pixelID];
cvt.u64.u32 %rd11, %r12;
cvt.u64.u32 %rd12, %r13;
// inline asm
call (%rd9), _rt_buffer_get_64, (%rd4, %r10, %r11, %rd11, %rd12, %rd20, %rd20);
// inline asm
ld.u16 %rs2, [%rd9+2];
// inline asm
{ cvt.f32.f16 %f14, %rs2;}
// inline asm
ld.global.v2.u32 {%r16, %r17}, [pixelID];
cvt.u64.u32 %rd17, %r16;
cvt.u64.u32 %rd18, %r17;
// inline asm
call (%rd15), _rt_buffer_get_64, (%rd4, %r10, %r11, %rd17, %rd18, %rd20, %rd20);
// inline asm
ld.u16 %rs3, [%rd15+4];
// inline asm
{ cvt.f32.f16 %f15, %rs3;}
// inline asm
BB0_3:
ld.global.v2.u32 {%r36, %r37}, [pixelID];
cvt.u64.u32 %rd43, %r36;
cvt.u64.u32 %rd44, %r37;
mov.u64 %rd47, input_buffer;
cvta.global.u64 %rd42, %rd47;
mov.u32 %r34, 2;
mov.u32 %r35, 12;
mov.u64 %rd46, 0;
// inline asm
call (%rd41), _rt_buffer_get_64, (%rd42, %r34, %r35, %rd43, %rd44, %rd46, %rd46);
// inline asm
st.f32 [%rd41+8], %f15;
st.f32 [%rd41+4], %f14;
st.f32 [%rd41], %f13;
ret;
}