599 lines
18 KiB
Plaintext
599 lines
18 KiB
Plaintext
//
|
|
// Generated by NVIDIA NVVM Compiler
|
|
//
|
|
// Compiler Build ID: CL-23083092
|
|
// Cuda compilation tools, release 9.1, V9.1.85
|
|
// Based on LLVM 3.4svn
|
|
//
|
|
|
|
.version 6.1
|
|
.target sm_30
|
|
.address_size 64
|
|
|
|
// .globl _Z6oxMainv
|
|
.global .align 8 .b8 pixelID[8];
|
|
.global .align 8 .b8 resolution[8];
|
|
.global .align 1 .b8 output_buffer[1];
|
|
.global .align 1 .b8 image2[1];
|
|
.global .align 1 .b8 image3[1];
|
|
.global .align 4 .u32 mode;
|
|
.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
|
|
.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
|
|
.global .align 4 .b8 _ZN21rti_internal_typeinfo4modeE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
|
|
.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
|
|
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
|
|
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
|
|
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
|
|
.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
|
|
.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
|
|
.global .align 4 .b8 _ZN21rti_internal_typename4modeE[4] = {105, 110, 116, 0};
|
|
.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
|
|
.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
|
|
.global .align 4 .u32 _ZN21rti_internal_typeenum4modeE = 4919;
|
|
.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
|
|
.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
|
|
.global .align 1 .b8 _ZN21rti_internal_semantic4modeE[1];
|
|
.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
|
|
.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
|
|
.global .align 1 .b8 _ZN23rti_internal_annotation4modeE[1];
|
|
|
|
.visible .entry _Z6oxMainv(
|
|
|
|
)
|
|
{
|
|
.reg .pred %p<53>;
|
|
.reg .b16 %rs<9>;
|
|
.reg .f32 %f<338>;
|
|
.reg .b32 %r<52>;
|
|
.reg .b64 %rd<24>;
|
|
|
|
|
|
ld.global.v2.u32 {%r3, %r4}, [pixelID];
|
|
cvt.u64.u32 %rd3, %r3;
|
|
cvt.u64.u32 %rd4, %r4;
|
|
mov.u64 %rd7, output_buffer;
|
|
cvta.global.u64 %rd2, %rd7;
|
|
mov.u32 %r1, 2;
|
|
mov.u32 %r2, 16;
|
|
mov.u64 %rd6, 0;
|
|
// inline asm
|
|
call (%rd1), _rt_buffer_get_64, (%rd2, %r1, %r2, %rd3, %rd4, %rd6, %rd6);
|
|
// inline asm
|
|
ld.v4.f32 {%f46, %f47, %f48, %f49}, [%rd1];
|
|
mov.f32 %f50, 0f3F8CCCCD;
|
|
cvt.rzi.f32.f32 %f51, %f50;
|
|
fma.rn.f32 %f52, %f51, 0fC0000000, 0f400CCCCD;
|
|
abs.f32 %f3, %f52;
|
|
abs.f32 %f5, %f46;
|
|
setp.lt.f32 %p4, %f5, 0f00800000;
|
|
mul.f32 %f53, %f5, 0f4B800000;
|
|
selp.f32 %f54, 0fC3170000, 0fC2FE0000, %p4;
|
|
selp.f32 %f55, %f53, %f5, %p4;
|
|
mov.b32 %r7, %f55;
|
|
and.b32 %r8, %r7, 8388607;
|
|
or.b32 %r9, %r8, 1065353216;
|
|
mov.b32 %f56, %r9;
|
|
shr.u32 %r10, %r7, 23;
|
|
cvt.rn.f32.u32 %f57, %r10;
|
|
add.f32 %f58, %f54, %f57;
|
|
setp.gt.f32 %p5, %f56, 0f3FB504F3;
|
|
mul.f32 %f59, %f56, 0f3F000000;
|
|
add.f32 %f60, %f58, 0f3F800000;
|
|
selp.f32 %f61, %f59, %f56, %p5;
|
|
selp.f32 %f62, %f60, %f58, %p5;
|
|
add.f32 %f63, %f61, 0fBF800000;
|
|
add.f32 %f45, %f61, 0f3F800000;
|
|
// inline asm
|
|
rcp.approx.ftz.f32 %f44,%f45;
|
|
// inline asm
|
|
add.f32 %f64, %f63, %f63;
|
|
mul.f32 %f65, %f44, %f64;
|
|
mul.f32 %f66, %f65, %f65;
|
|
mov.f32 %f67, 0f3C4CAF63;
|
|
mov.f32 %f68, 0f3B18F0FE;
|
|
fma.rn.f32 %f69, %f68, %f66, %f67;
|
|
mov.f32 %f70, 0f3DAAAABD;
|
|
fma.rn.f32 %f71, %f69, %f66, %f70;
|
|
mul.rn.f32 %f72, %f71, %f66;
|
|
mul.rn.f32 %f73, %f72, %f65;
|
|
sub.f32 %f74, %f63, %f65;
|
|
neg.f32 %f75, %f65;
|
|
add.f32 %f76, %f74, %f74;
|
|
fma.rn.f32 %f77, %f75, %f63, %f76;
|
|
mul.rn.f32 %f78, %f44, %f77;
|
|
add.f32 %f79, %f73, %f65;
|
|
sub.f32 %f80, %f65, %f79;
|
|
add.f32 %f81, %f73, %f80;
|
|
add.f32 %f82, %f78, %f81;
|
|
add.f32 %f83, %f79, %f82;
|
|
sub.f32 %f84, %f79, %f83;
|
|
add.f32 %f85, %f82, %f84;
|
|
mov.f32 %f86, 0f3F317200;
|
|
mul.rn.f32 %f87, %f62, %f86;
|
|
mov.f32 %f88, 0f35BFBE8E;
|
|
mul.rn.f32 %f89, %f62, %f88;
|
|
add.f32 %f90, %f87, %f83;
|
|
sub.f32 %f91, %f87, %f90;
|
|
add.f32 %f92, %f83, %f91;
|
|
add.f32 %f93, %f85, %f92;
|
|
add.f32 %f94, %f89, %f93;
|
|
add.f32 %f95, %f90, %f94;
|
|
sub.f32 %f96, %f90, %f95;
|
|
add.f32 %f97, %f94, %f96;
|
|
mov.f32 %f98, 0f400CCCCD;
|
|
mul.rn.f32 %f99, %f98, %f95;
|
|
neg.f32 %f100, %f99;
|
|
fma.rn.f32 %f101, %f98, %f95, %f100;
|
|
fma.rn.f32 %f102, %f98, %f97, %f101;
|
|
mov.f32 %f103, 0f00000000;
|
|
fma.rn.f32 %f104, %f103, %f95, %f102;
|
|
add.rn.f32 %f105, %f99, %f104;
|
|
neg.f32 %f106, %f105;
|
|
add.rn.f32 %f107, %f99, %f106;
|
|
add.rn.f32 %f108, %f107, %f104;
|
|
mov.b32 %r11, %f105;
|
|
setp.eq.s32 %p6, %r11, 1118925336;
|
|
add.s32 %r12, %r11, -1;
|
|
mov.b32 %f109, %r12;
|
|
add.f32 %f110, %f108, 0f37000000;
|
|
selp.f32 %f111, %f109, %f105, %p6;
|
|
selp.f32 %f6, %f110, %f108, %p6;
|
|
mul.f32 %f112, %f111, 0f3FB8AA3B;
|
|
cvt.rzi.f32.f32 %f113, %f112;
|
|
mov.f32 %f114, 0fBF317200;
|
|
fma.rn.f32 %f115, %f113, %f114, %f111;
|
|
mov.f32 %f116, 0fB5BFBE8E;
|
|
fma.rn.f32 %f117, %f113, %f116, %f115;
|
|
mul.f32 %f118, %f117, 0f3FB8AA3B;
|
|
ex2.approx.ftz.f32 %f119, %f118;
|
|
add.f32 %f120, %f113, 0f00000000;
|
|
ex2.approx.f32 %f121, %f120;
|
|
mul.f32 %f122, %f119, %f121;
|
|
setp.lt.f32 %p7, %f111, 0fC2D20000;
|
|
selp.f32 %f123, 0f00000000, %f122, %p7;
|
|
setp.gt.f32 %p8, %f111, 0f42D20000;
|
|
selp.f32 %f329, 0f7F800000, %f123, %p8;
|
|
setp.eq.f32 %p9, %f329, 0f7F800000;
|
|
@%p9 bra BB0_2;
|
|
|
|
fma.rn.f32 %f329, %f329, %f6, %f329;
|
|
|
|
BB0_2:
|
|
setp.lt.f32 %p10, %f46, 0f00000000;
|
|
setp.eq.f32 %p11, %f3, 0f3F800000;
|
|
and.pred %p1, %p10, %p11;
|
|
mov.b32 %r13, %f329;
|
|
xor.b32 %r14, %r13, -2147483648;
|
|
mov.b32 %f124, %r14;
|
|
selp.f32 %f331, %f124, %f329, %p1;
|
|
setp.eq.f32 %p12, %f46, 0f00000000;
|
|
@%p12 bra BB0_5;
|
|
bra.uni BB0_3;
|
|
|
|
BB0_5:
|
|
add.f32 %f127, %f46, %f46;
|
|
selp.f32 %f331, %f127, 0f00000000, %p11;
|
|
bra.uni BB0_6;
|
|
|
|
BB0_3:
|
|
setp.geu.f32 %p13, %f46, 0f00000000;
|
|
@%p13 bra BB0_6;
|
|
|
|
mov.f32 %f328, 0f400CCCCD;
|
|
cvt.rzi.f32.f32 %f126, %f328;
|
|
setp.neu.f32 %p14, %f126, 0f400CCCCD;
|
|
selp.f32 %f331, 0f7FFFFFFF, %f331, %p14;
|
|
|
|
BB0_6:
|
|
abs.f32 %f305, %f46;
|
|
add.f32 %f128, %f305, 0f400CCCCD;
|
|
mov.b32 %r15, %f128;
|
|
setp.lt.s32 %p16, %r15, 2139095040;
|
|
@%p16 bra BB0_11;
|
|
|
|
abs.f32 %f326, %f46;
|
|
setp.gtu.f32 %p17, %f326, 0f7F800000;
|
|
@%p17 bra BB0_10;
|
|
bra.uni BB0_8;
|
|
|
|
BB0_10:
|
|
add.f32 %f331, %f46, 0f400CCCCD;
|
|
bra.uni BB0_11;
|
|
|
|
BB0_8:
|
|
abs.f32 %f327, %f46;
|
|
setp.neu.f32 %p18, %f327, 0f7F800000;
|
|
@%p18 bra BB0_11;
|
|
|
|
selp.f32 %f331, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
BB0_11:
|
|
mov.f32 %f314, 0fB5BFBE8E;
|
|
mov.f32 %f313, 0fBF317200;
|
|
mov.f32 %f312, 0f00000000;
|
|
mov.f32 %f311, 0f35BFBE8E;
|
|
mov.f32 %f310, 0f3F317200;
|
|
mov.f32 %f309, 0f3DAAAABD;
|
|
mov.f32 %f308, 0f3C4CAF63;
|
|
mov.f32 %f307, 0f3B18F0FE;
|
|
mov.f32 %f306, 0f400CCCCD;
|
|
setp.eq.f32 %p19, %f46, 0f3F800000;
|
|
selp.f32 %f131, 0f3F800000, %f331, %p19;
|
|
cvt.sat.f32.f32 %f17, %f131;
|
|
abs.f32 %f18, %f47;
|
|
setp.lt.f32 %p20, %f18, 0f00800000;
|
|
mul.f32 %f132, %f18, 0f4B800000;
|
|
selp.f32 %f133, 0fC3170000, 0fC2FE0000, %p20;
|
|
selp.f32 %f134, %f132, %f18, %p20;
|
|
mov.b32 %r16, %f134;
|
|
and.b32 %r17, %r16, 8388607;
|
|
or.b32 %r18, %r17, 1065353216;
|
|
mov.b32 %f135, %r18;
|
|
shr.u32 %r19, %r16, 23;
|
|
cvt.rn.f32.u32 %f136, %r19;
|
|
add.f32 %f137, %f133, %f136;
|
|
setp.gt.f32 %p21, %f135, 0f3FB504F3;
|
|
mul.f32 %f138, %f135, 0f3F000000;
|
|
add.f32 %f139, %f137, 0f3F800000;
|
|
selp.f32 %f140, %f138, %f135, %p21;
|
|
selp.f32 %f141, %f139, %f137, %p21;
|
|
add.f32 %f142, %f140, 0fBF800000;
|
|
add.f32 %f130, %f140, 0f3F800000;
|
|
// inline asm
|
|
rcp.approx.ftz.f32 %f129,%f130;
|
|
// inline asm
|
|
add.f32 %f143, %f142, %f142;
|
|
mul.f32 %f144, %f129, %f143;
|
|
mul.f32 %f145, %f144, %f144;
|
|
fma.rn.f32 %f148, %f307, %f145, %f308;
|
|
fma.rn.f32 %f150, %f148, %f145, %f309;
|
|
mul.rn.f32 %f151, %f150, %f145;
|
|
mul.rn.f32 %f152, %f151, %f144;
|
|
sub.f32 %f153, %f142, %f144;
|
|
neg.f32 %f154, %f144;
|
|
add.f32 %f155, %f153, %f153;
|
|
fma.rn.f32 %f156, %f154, %f142, %f155;
|
|
mul.rn.f32 %f157, %f129, %f156;
|
|
add.f32 %f158, %f152, %f144;
|
|
sub.f32 %f159, %f144, %f158;
|
|
add.f32 %f160, %f152, %f159;
|
|
add.f32 %f161, %f157, %f160;
|
|
add.f32 %f162, %f158, %f161;
|
|
sub.f32 %f163, %f158, %f162;
|
|
add.f32 %f164, %f161, %f163;
|
|
mul.rn.f32 %f166, %f141, %f310;
|
|
mul.rn.f32 %f168, %f141, %f311;
|
|
add.f32 %f169, %f166, %f162;
|
|
sub.f32 %f170, %f166, %f169;
|
|
add.f32 %f171, %f162, %f170;
|
|
add.f32 %f172, %f164, %f171;
|
|
add.f32 %f173, %f168, %f172;
|
|
add.f32 %f174, %f169, %f173;
|
|
sub.f32 %f175, %f169, %f174;
|
|
add.f32 %f176, %f173, %f175;
|
|
mul.rn.f32 %f178, %f306, %f174;
|
|
neg.f32 %f179, %f178;
|
|
fma.rn.f32 %f180, %f306, %f174, %f179;
|
|
fma.rn.f32 %f181, %f306, %f176, %f180;
|
|
fma.rn.f32 %f183, %f312, %f174, %f181;
|
|
add.rn.f32 %f184, %f178, %f183;
|
|
neg.f32 %f185, %f184;
|
|
add.rn.f32 %f186, %f178, %f185;
|
|
add.rn.f32 %f187, %f186, %f183;
|
|
mov.b32 %r20, %f184;
|
|
setp.eq.s32 %p22, %r20, 1118925336;
|
|
add.s32 %r21, %r20, -1;
|
|
mov.b32 %f188, %r21;
|
|
add.f32 %f189, %f187, 0f37000000;
|
|
selp.f32 %f190, %f188, %f184, %p22;
|
|
selp.f32 %f19, %f189, %f187, %p22;
|
|
mul.f32 %f191, %f190, 0f3FB8AA3B;
|
|
cvt.rzi.f32.f32 %f192, %f191;
|
|
fma.rn.f32 %f194, %f192, %f313, %f190;
|
|
fma.rn.f32 %f196, %f192, %f314, %f194;
|
|
mul.f32 %f197, %f196, 0f3FB8AA3B;
|
|
ex2.approx.ftz.f32 %f198, %f197;
|
|
add.f32 %f199, %f192, 0f00000000;
|
|
ex2.approx.f32 %f200, %f199;
|
|
mul.f32 %f201, %f198, %f200;
|
|
setp.lt.f32 %p23, %f190, 0fC2D20000;
|
|
selp.f32 %f202, 0f00000000, %f201, %p23;
|
|
setp.gt.f32 %p24, %f190, 0f42D20000;
|
|
selp.f32 %f332, 0f7F800000, %f202, %p24;
|
|
setp.eq.f32 %p25, %f332, 0f7F800000;
|
|
@%p25 bra BB0_13;
|
|
|
|
fma.rn.f32 %f332, %f332, %f19, %f332;
|
|
|
|
BB0_13:
|
|
setp.lt.f32 %p26, %f47, 0f00000000;
|
|
and.pred %p2, %p26, %p11;
|
|
mov.b32 %r22, %f332;
|
|
xor.b32 %r23, %r22, -2147483648;
|
|
mov.b32 %f203, %r23;
|
|
selp.f32 %f334, %f203, %f332, %p2;
|
|
setp.eq.f32 %p28, %f47, 0f00000000;
|
|
@%p28 bra BB0_16;
|
|
bra.uni BB0_14;
|
|
|
|
BB0_16:
|
|
add.f32 %f206, %f47, %f47;
|
|
selp.f32 %f334, %f206, 0f00000000, %p11;
|
|
bra.uni BB0_17;
|
|
|
|
BB0_14:
|
|
setp.geu.f32 %p29, %f47, 0f00000000;
|
|
@%p29 bra BB0_17;
|
|
|
|
mov.f32 %f325, 0f400CCCCD;
|
|
cvt.rzi.f32.f32 %f205, %f325;
|
|
setp.neu.f32 %p30, %f205, 0f400CCCCD;
|
|
selp.f32 %f334, 0f7FFFFFFF, %f334, %p30;
|
|
|
|
BB0_17:
|
|
add.f32 %f207, %f18, 0f400CCCCD;
|
|
mov.b32 %r24, %f207;
|
|
setp.lt.s32 %p32, %r24, 2139095040;
|
|
@%p32 bra BB0_22;
|
|
|
|
setp.gtu.f32 %p33, %f18, 0f7F800000;
|
|
@%p33 bra BB0_21;
|
|
bra.uni BB0_19;
|
|
|
|
BB0_21:
|
|
add.f32 %f334, %f47, 0f400CCCCD;
|
|
bra.uni BB0_22;
|
|
|
|
BB0_19:
|
|
setp.neu.f32 %p34, %f18, 0f7F800000;
|
|
@%p34 bra BB0_22;
|
|
|
|
selp.f32 %f334, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
BB0_22:
|
|
mov.f32 %f323, 0fB5BFBE8E;
|
|
mov.f32 %f322, 0fBF317200;
|
|
mov.f32 %f321, 0f00000000;
|
|
mov.f32 %f320, 0f35BFBE8E;
|
|
mov.f32 %f319, 0f3F317200;
|
|
mov.f32 %f318, 0f3DAAAABD;
|
|
mov.f32 %f317, 0f3C4CAF63;
|
|
mov.f32 %f316, 0f3B18F0FE;
|
|
mov.f32 %f315, 0f400CCCCD;
|
|
setp.eq.f32 %p35, %f47, 0f3F800000;
|
|
selp.f32 %f210, 0f3F800000, %f334, %p35;
|
|
cvt.sat.f32.f32 %f30, %f210;
|
|
abs.f32 %f31, %f48;
|
|
setp.lt.f32 %p36, %f31, 0f00800000;
|
|
mul.f32 %f211, %f31, 0f4B800000;
|
|
selp.f32 %f212, 0fC3170000, 0fC2FE0000, %p36;
|
|
selp.f32 %f213, %f211, %f31, %p36;
|
|
mov.b32 %r25, %f213;
|
|
and.b32 %r26, %r25, 8388607;
|
|
or.b32 %r27, %r26, 1065353216;
|
|
mov.b32 %f214, %r27;
|
|
shr.u32 %r28, %r25, 23;
|
|
cvt.rn.f32.u32 %f215, %r28;
|
|
add.f32 %f216, %f212, %f215;
|
|
setp.gt.f32 %p37, %f214, 0f3FB504F3;
|
|
mul.f32 %f217, %f214, 0f3F000000;
|
|
add.f32 %f218, %f216, 0f3F800000;
|
|
selp.f32 %f219, %f217, %f214, %p37;
|
|
selp.f32 %f220, %f218, %f216, %p37;
|
|
add.f32 %f221, %f219, 0fBF800000;
|
|
add.f32 %f209, %f219, 0f3F800000;
|
|
// inline asm
|
|
rcp.approx.ftz.f32 %f208,%f209;
|
|
// inline asm
|
|
add.f32 %f222, %f221, %f221;
|
|
mul.f32 %f223, %f208, %f222;
|
|
mul.f32 %f224, %f223, %f223;
|
|
fma.rn.f32 %f227, %f316, %f224, %f317;
|
|
fma.rn.f32 %f229, %f227, %f224, %f318;
|
|
mul.rn.f32 %f230, %f229, %f224;
|
|
mul.rn.f32 %f231, %f230, %f223;
|
|
sub.f32 %f232, %f221, %f223;
|
|
neg.f32 %f233, %f223;
|
|
add.f32 %f234, %f232, %f232;
|
|
fma.rn.f32 %f235, %f233, %f221, %f234;
|
|
mul.rn.f32 %f236, %f208, %f235;
|
|
add.f32 %f237, %f231, %f223;
|
|
sub.f32 %f238, %f223, %f237;
|
|
add.f32 %f239, %f231, %f238;
|
|
add.f32 %f240, %f236, %f239;
|
|
add.f32 %f241, %f237, %f240;
|
|
sub.f32 %f242, %f237, %f241;
|
|
add.f32 %f243, %f240, %f242;
|
|
mul.rn.f32 %f245, %f220, %f319;
|
|
mul.rn.f32 %f247, %f220, %f320;
|
|
add.f32 %f248, %f245, %f241;
|
|
sub.f32 %f249, %f245, %f248;
|
|
add.f32 %f250, %f241, %f249;
|
|
add.f32 %f251, %f243, %f250;
|
|
add.f32 %f252, %f247, %f251;
|
|
add.f32 %f253, %f248, %f252;
|
|
sub.f32 %f254, %f248, %f253;
|
|
add.f32 %f255, %f252, %f254;
|
|
mul.rn.f32 %f257, %f315, %f253;
|
|
neg.f32 %f258, %f257;
|
|
fma.rn.f32 %f259, %f315, %f253, %f258;
|
|
fma.rn.f32 %f260, %f315, %f255, %f259;
|
|
fma.rn.f32 %f262, %f321, %f253, %f260;
|
|
add.rn.f32 %f263, %f257, %f262;
|
|
neg.f32 %f264, %f263;
|
|
add.rn.f32 %f265, %f257, %f264;
|
|
add.rn.f32 %f266, %f265, %f262;
|
|
mov.b32 %r29, %f263;
|
|
setp.eq.s32 %p38, %r29, 1118925336;
|
|
add.s32 %r30, %r29, -1;
|
|
mov.b32 %f267, %r30;
|
|
add.f32 %f268, %f266, 0f37000000;
|
|
selp.f32 %f269, %f267, %f263, %p38;
|
|
selp.f32 %f32, %f268, %f266, %p38;
|
|
mul.f32 %f270, %f269, 0f3FB8AA3B;
|
|
cvt.rzi.f32.f32 %f271, %f270;
|
|
fma.rn.f32 %f273, %f271, %f322, %f269;
|
|
fma.rn.f32 %f275, %f271, %f323, %f273;
|
|
mul.f32 %f276, %f275, 0f3FB8AA3B;
|
|
ex2.approx.ftz.f32 %f277, %f276;
|
|
add.f32 %f278, %f271, 0f00000000;
|
|
ex2.approx.f32 %f279, %f278;
|
|
mul.f32 %f280, %f277, %f279;
|
|
setp.lt.f32 %p39, %f269, 0fC2D20000;
|
|
selp.f32 %f281, 0f00000000, %f280, %p39;
|
|
setp.gt.f32 %p40, %f269, 0f42D20000;
|
|
selp.f32 %f335, 0f7F800000, %f281, %p40;
|
|
setp.eq.f32 %p41, %f335, 0f7F800000;
|
|
@%p41 bra BB0_24;
|
|
|
|
fma.rn.f32 %f335, %f335, %f32, %f335;
|
|
|
|
BB0_24:
|
|
setp.lt.f32 %p42, %f48, 0f00000000;
|
|
and.pred %p3, %p42, %p11;
|
|
mov.b32 %r31, %f335;
|
|
xor.b32 %r32, %r31, -2147483648;
|
|
mov.b32 %f282, %r32;
|
|
selp.f32 %f337, %f282, %f335, %p3;
|
|
setp.eq.f32 %p44, %f48, 0f00000000;
|
|
@%p44 bra BB0_27;
|
|
bra.uni BB0_25;
|
|
|
|
BB0_27:
|
|
add.f32 %f285, %f48, %f48;
|
|
selp.f32 %f337, %f285, 0f00000000, %p11;
|
|
bra.uni BB0_28;
|
|
|
|
BB0_25:
|
|
setp.geu.f32 %p45, %f48, 0f00000000;
|
|
@%p45 bra BB0_28;
|
|
|
|
mov.f32 %f324, 0f400CCCCD;
|
|
cvt.rzi.f32.f32 %f284, %f324;
|
|
setp.neu.f32 %p46, %f284, 0f400CCCCD;
|
|
selp.f32 %f337, 0f7FFFFFFF, %f337, %p46;
|
|
|
|
BB0_28:
|
|
add.f32 %f286, %f31, 0f400CCCCD;
|
|
mov.b32 %r33, %f286;
|
|
setp.lt.s32 %p48, %r33, 2139095040;
|
|
@%p48 bra BB0_33;
|
|
|
|
setp.gtu.f32 %p49, %f31, 0f7F800000;
|
|
@%p49 bra BB0_32;
|
|
bra.uni BB0_30;
|
|
|
|
BB0_32:
|
|
add.f32 %f337, %f48, 0f400CCCCD;
|
|
bra.uni BB0_33;
|
|
|
|
BB0_30:
|
|
setp.neu.f32 %p50, %f31, 0f7F800000;
|
|
@%p50 bra BB0_33;
|
|
|
|
selp.f32 %f337, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
BB0_33:
|
|
setp.eq.f32 %p51, %f48, 0f3F800000;
|
|
selp.f32 %f287, 0f3F800000, %f337, %p51;
|
|
cvt.sat.f32.f32 %f43, %f287;
|
|
ld.global.u32 %r34, [mode];
|
|
setp.gt.s32 %p52, %r34, 0;
|
|
@%p52 bra BB0_35;
|
|
bra.uni BB0_34;
|
|
|
|
BB0_35:
|
|
mov.u64 %rd23, 0;
|
|
mov.u32 %r51, 2;
|
|
ld.global.v2.u32 {%r43, %r44}, [pixelID];
|
|
cvt.u64.u32 %rd17, %r43;
|
|
cvt.u64.u32 %rd18, %r44;
|
|
mov.u64 %rd21, image3;
|
|
cvta.global.u64 %rd16, %rd21;
|
|
mov.u32 %r42, 4;
|
|
// inline asm
|
|
call (%rd15), _rt_buffer_get_64, (%rd16, %r51, %r42, %rd17, %rd18, %rd23, %rd23);
|
|
// inline asm
|
|
cvt.sat.f32.f32 %f299, %f17;
|
|
mul.f32 %f300, %f299, 0f437F0000;
|
|
cvt.rzi.u32.f32 %r47, %f300;
|
|
cvt.sat.f32.f32 %f301, %f30;
|
|
mul.f32 %f302, %f301, 0f437F0000;
|
|
cvt.rzi.u32.f32 %r48, %f302;
|
|
cvt.sat.f32.f32 %f303, %f43;
|
|
mul.f32 %f304, %f303, 0f437F0000;
|
|
cvt.rzi.u32.f32 %r49, %f304;
|
|
cvt.u16.u32 %rs5, %r49;
|
|
cvt.u16.u32 %rs6, %r48;
|
|
cvt.u16.u32 %rs7, %r47;
|
|
mov.u16 %rs8, 255;
|
|
st.v4.u8 [%rd15], {%rs7, %rs6, %rs5, %rs8};
|
|
bra.uni BB0_36;
|
|
|
|
BB0_34:
|
|
mov.u64 %rd22, 0;
|
|
mov.u32 %r50, 2;
|
|
max.f32 %f292, %f17, %f30;
|
|
max.f32 %f293, %f292, %f43;
|
|
mov.f32 %f291, 0f3F800000;
|
|
sub.f32 %f294, %f291, %f293;
|
|
rcp.rn.f32 %f295, %f294;
|
|
mul.f32 %f296, %f17, %f295;
|
|
mul.f32 %f297, %f30, %f295;
|
|
mul.f32 %f298, %f43, %f295;
|
|
mul.f32 %f288, %f296, 0f3E800000;
|
|
mul.f32 %f289, %f297, 0f3E800000;
|
|
mul.f32 %f290, %f298, 0f3E800000;
|
|
ld.global.v2.u32 {%r37, %r38}, [pixelID];
|
|
cvt.u64.u32 %rd10, %r37;
|
|
cvt.u64.u32 %rd11, %r38;
|
|
mov.u64 %rd14, image2;
|
|
cvta.global.u64 %rd9, %rd14;
|
|
mov.u32 %r36, 8;
|
|
// inline asm
|
|
call (%rd8), _rt_buffer_get_64, (%rd9, %r50, %r36, %rd10, %rd11, %rd22, %rd22);
|
|
// inline asm
|
|
// inline asm
|
|
{ cvt.rn.f16.f32 %rs3, %f290;}
|
|
|
|
// inline asm
|
|
// inline asm
|
|
{ cvt.rn.f16.f32 %rs2, %f289;}
|
|
|
|
// inline asm
|
|
// inline asm
|
|
{ cvt.rn.f16.f32 %rs1, %f288;}
|
|
|
|
// inline asm
|
|
// inline asm
|
|
{ cvt.rn.f16.f32 %rs4, %f291;}
|
|
|
|
// inline asm
|
|
st.v4.u16 [%rd8], {%rs1, %rs2, %rs3, %rs4};
|
|
|
|
BB0_36:
|
|
ret;
|
|
}
|
|
|
|
|