217 lines
8.4 KiB
Plaintext
217 lines
8.4 KiB
Plaintext
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//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-23083092
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// Cuda compilation tools, release 9.1, V9.1.85
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// Based on LLVM 3.4svn
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//
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.version 6.1
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.target sm_30
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.address_size 64
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// .globl _Z6oxMainv
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.global .align 8 .b8 pixelID[8];
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.global .align 8 .b8 resolution[8];
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.global .align 4 .b8 normal[12];
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.global .align 4 .b8 camPos[12];
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.global .align 4 .b8 root[4];
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.global .align 4 .u32 imageEnabled;
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.global .texref lightmap;
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.global .align 16 .b8 tileInfo[16];
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.global .align 4 .u32 additive;
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.global .align 1 .b8 image[1];
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.global .align 1 .b8 image2[1];
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.global .align 1 .b8 image3[1];
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.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo6normalE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo6camPosE[8] = {82, 97, 121, 0, 12, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo4rootE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo12imageEnabledE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo8tileInfoE[8] = {82, 97, 121, 0, 16, 0, 0, 0};
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.global .align 4 .b8 _ZN21rti_internal_typeinfo8additiveE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
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.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
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.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
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.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
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.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
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.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
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.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
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.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
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.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
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.global .align 8 .b8 _ZN21rti_internal_typename6normalE[7] = {102, 108, 111, 97, 116, 51, 0};
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.global .align 8 .b8 _ZN21rti_internal_typename6camPosE[7] = {102, 108, 111, 97, 116, 51, 0};
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.global .align 16 .b8 _ZN21rti_internal_typename4rootE[9] = {114, 116, 79, 98, 106, 101, 99, 116, 0};
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.global .align 4 .b8 _ZN21rti_internal_typename12imageEnabledE[4] = {105, 110, 116, 0};
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.global .align 8 .b8 _ZN21rti_internal_typename8tileInfoE[6] = {117, 105, 110, 116, 52, 0};
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.global .align 4 .b8 _ZN21rti_internal_typename8additiveE[4] = {105, 110, 116, 0};
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.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum6normalE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum6camPosE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum4rootE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum12imageEnabledE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum8tileInfoE = 4919;
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.global .align 4 .u32 _ZN21rti_internal_typeenum8additiveE = 4919;
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.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
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.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
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.global .align 16 .b8 _ZN21rti_internal_semantic6normalE[17] = {97, 116, 116, 114, 105, 98, 117, 116, 101, 32, 110, 111, 114, 109, 97, 108, 0};
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.global .align 1 .b8 _ZN21rti_internal_semantic6camPosE[1];
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.global .align 1 .b8 _ZN21rti_internal_semantic4rootE[1];
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.global .align 1 .b8 _ZN21rti_internal_semantic12imageEnabledE[1];
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.global .align 1 .b8 _ZN21rti_internal_semantic8tileInfoE[1];
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.global .align 1 .b8 _ZN21rti_internal_semantic8additiveE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation6normalE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation6camPosE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation4rootE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation12imageEnabledE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation8tileInfoE[1];
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.global .align 1 .b8 _ZN23rti_internal_annotation8additiveE[1];
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.visible .entry _Z6oxMainv(
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)
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{
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.reg .b16 %rs<12>;
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.reg .f32 %f<12>;
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.reg .b32 %r<49>;
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.reg .b64 %rd<52>;
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ld.global.v2.u32 {%r17, %r18}, [pixelID];
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cvt.u64.u32 %rd3, %r17;
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cvt.u64.u32 %rd4, %r18;
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mov.u64 %rd49, image;
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cvta.global.u64 %rd2, %rd49;
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mov.u32 %r15, 2;
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mov.u32 %r16, 8;
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mov.u64 %rd48, 0;
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// inline asm
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call (%rd1), _rt_buffer_get_64, (%rd2, %r15, %r16, %rd3, %rd4, %rd48, %rd48);
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// inline asm
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ld.u16 %rs1, [%rd1+6];
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// inline asm
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{ cvt.f32.f16 %f1, %rs1;}
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// inline asm
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ld.global.v2.u32 {%r21, %r22}, [pixelID];
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cvt.u64.u32 %rd9, %r21;
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cvt.u64.u32 %rd10, %r22;
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// inline asm
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call (%rd7), _rt_buffer_get_64, (%rd2, %r15, %r16, %rd9, %rd10, %rd48, %rd48);
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// inline asm
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ld.u16 %rs2, [%rd7];
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// inline asm
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{ cvt.f32.f16 %f2, %rs2;}
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// inline asm
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ld.global.v2.u32 {%r25, %r26}, [pixelID];
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cvt.u64.u32 %rd15, %r25;
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cvt.u64.u32 %rd16, %r26;
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// inline asm
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call (%rd13), _rt_buffer_get_64, (%rd2, %r15, %r16, %rd15, %rd16, %rd48, %rd48);
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// inline asm
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ld.u16 %rs3, [%rd13+2];
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// inline asm
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{ cvt.f32.f16 %f3, %rs3;}
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// inline asm
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ld.global.v2.u32 {%r29, %r30}, [pixelID];
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cvt.u64.u32 %rd21, %r29;
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cvt.u64.u32 %rd22, %r30;
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// inline asm
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call (%rd19), _rt_buffer_get_64, (%rd2, %r15, %r16, %rd21, %rd22, %rd48, %rd48);
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// inline asm
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ld.u16 %rs4, [%rd19+4];
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// inline asm
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{ cvt.f32.f16 %f4, %rs4;}
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// inline asm
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ld.global.v2.u32 {%r33, %r34}, [pixelID];
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cvt.u64.u32 %rd27, %r33;
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cvt.u64.u32 %rd28, %r34;
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mov.u64 %rd50, image3;
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cvta.global.u64 %rd26, %rd50;
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// inline asm
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call (%rd25), _rt_buffer_get_64, (%rd26, %r15, %r16, %rd27, %rd28, %rd48, %rd48);
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// inline asm
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ld.u16 %rs5, [%rd25];
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// inline asm
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{ cvt.f32.f16 %f5, %rs5;}
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// inline asm
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ld.global.v2.u32 {%r37, %r38}, [pixelID];
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cvt.u64.u32 %rd33, %r37;
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cvt.u64.u32 %rd34, %r38;
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// inline asm
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call (%rd31), _rt_buffer_get_64, (%rd26, %r15, %r16, %rd33, %rd34, %rd48, %rd48);
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// inline asm
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ld.u16 %rs6, [%rd31+2];
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// inline asm
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{ cvt.f32.f16 %f6, %rs6;}
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// inline asm
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ld.global.v2.u32 {%r41, %r42}, [pixelID];
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cvt.u64.u32 %rd39, %r41;
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cvt.u64.u32 %rd40, %r42;
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// inline asm
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call (%rd37), _rt_buffer_get_64, (%rd26, %r15, %r16, %rd39, %rd40, %rd48, %rd48);
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// inline asm
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ld.u16 %rs7, [%rd37+4];
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// inline asm
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{ cvt.f32.f16 %f7, %rs7;}
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// inline asm
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sub.f32 %f8, %f2, %f5;
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sub.f32 %f9, %f3, %f6;
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sub.f32 %f10, %f4, %f7;
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ld.global.v2.u32 {%r45, %r46}, [pixelID];
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cvt.u64.u32 %rd45, %r45;
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cvt.u64.u32 %rd46, %r46;
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mov.u64 %rd51, image2;
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cvta.global.u64 %rd44, %rd51;
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// inline asm
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call (%rd43), _rt_buffer_get_64, (%rd44, %r15, %r16, %rd45, %rd46, %rd48, %rd48);
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs10, %f10;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs9, %f9;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs8, %f8;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs11, %f1;}
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// inline asm
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st.v4.u16 [%rd43], {%rs8, %rs9, %rs10, %rs11};
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ret;
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}
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