168 lines
5.9 KiB
Plaintext
168 lines
5.9 KiB
Plaintext
|
//
|
||
|
|
// Generated by NVIDIA NVVM Compiler
|
||
|
|
//
|
||
|
|
// Compiler Build ID: CL-23083092
|
||
|
|
// Cuda compilation tools, release 9.1, V9.1.85
|
||
|
|
// Based on LLVM 3.4svn
|
||
|
|
//
|
||
|
|
|
||
|
|
.version 6.1
|
||
|
|
.target sm_30
|
||
|
|
.address_size 64
|
||
|
|
|
||
|
|
// .globl _Z6oxMainv
|
||
|
|
.global .align 8 .b8 pixelID[8];
|
||
|
|
.global .align 8 .b8 resolution[8];
|
||
|
|
.global .align 1 .b8 output_buffer[1];
|
||
|
|
.global .align 1 .b8 image2[1];
|
||
|
|
.global .align 1 .b8 image3[1];
|
||
|
|
.global .align 4 .u32 mode;
|
||
|
|
.global .align 4 .b8 _ZN21rti_internal_typeinfo7pixelIDE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
|
||
|
|
.global .align 4 .b8 _ZN21rti_internal_typeinfo10resolutionE[8] = {82, 97, 121, 0, 8, 0, 0, 0};
|
||
|
|
.global .align 4 .b8 _ZN21rti_internal_typeinfo4modeE[8] = {82, 97, 121, 0, 4, 0, 0, 0};
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register20reg_bitness_detectorE;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail0E;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail1E;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail2E;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail3E;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail4E;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail5E;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail6E;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail7E;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail8E;
|
||
|
|
.global .align 8 .u64 _ZN21rti_internal_register24reg_exception_64_detail9E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail0E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail1E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail2E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail3E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail4E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail5E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail6E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail7E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail8E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register21reg_exception_detail9E;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_xE;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_yE;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_register14reg_rayIndex_zE;
|
||
|
|
.global .align 8 .b8 _ZN21rti_internal_typename7pixelIDE[6] = {117, 105, 110, 116, 50, 0};
|
||
|
|
.global .align 8 .b8 _ZN21rti_internal_typename10resolutionE[6] = {117, 105, 110, 116, 50, 0};
|
||
|
|
.global .align 4 .b8 _ZN21rti_internal_typename4modeE[4] = {105, 110, 116, 0};
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_typeenum7pixelIDE = 4919;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_typeenum10resolutionE = 4919;
|
||
|
|
.global .align 4 .u32 _ZN21rti_internal_typeenum4modeE = 4919;
|
||
|
|
.global .align 16 .b8 _ZN21rti_internal_semantic7pixelIDE[14] = {114, 116, 76, 97, 117, 110, 99, 104, 73, 110, 100, 101, 120, 0};
|
||
|
|
.global .align 16 .b8 _ZN21rti_internal_semantic10resolutionE[12] = {114, 116, 76, 97, 117, 110, 99, 104, 68, 105, 109, 0};
|
||
|
|
.global .align 1 .b8 _ZN21rti_internal_semantic4modeE[1];
|
||
|
|
.global .align 1 .b8 _ZN23rti_internal_annotation7pixelIDE[1];
|
||
|
|
.global .align 1 .b8 _ZN23rti_internal_annotation10resolutionE[1];
|
||
|
|
.global .align 1 .b8 _ZN23rti_internal_annotation4modeE[1];
|
||
|
|
|
||
|
|
.visible .entry _Z6oxMainv(
|
||
|
|
|
||
|
|
)
|
||
|
|
{
|
||
|
|
.reg .pred %p<2>;
|
||
|
|
.reg .b16 %rs<12>;
|
||
|
|
.reg .f32 %f<17>;
|
||
|
|
.reg .b32 %r<37>;
|
||
|
|
.reg .b64 %rd<43>;
|
||
|
|
|
||
|
|
|
||
|
|
ld.global.v2.u32 {%r3, %r4}, [pixelID];
|
||
|
|
cvt.u64.u32 %rd5, %r3;
|
||
|
|
cvt.u64.u32 %rd6, %r4;
|
||
|
|
mov.u64 %rd9, output_buffer;
|
||
|
|
cvta.global.u64 %rd4, %rd9;
|
||
|
|
mov.u32 %r1, 2;
|
||
|
|
mov.u32 %r2, 12;
|
||
|
|
mov.u64 %rd8, 0;
|
||
|
|
// inline asm
|
||
|
|
call (%rd3), _rt_buffer_get_64, (%rd4, %r1, %r2, %rd5, %rd6, %rd8, %rd8);
|
||
|
|
// inline asm
|
||
|
|
ld.f32 %f1, [%rd3];
|
||
|
|
ld.f32 %f2, [%rd3+4];
|
||
|
|
ld.f32 %f3, [%rd3+8];
|
||
|
|
ld.global.u32 %r7, [mode];
|
||
|
|
setp.gt.s32 %p1, %r7, 0;
|
||
|
|
ld.global.v2.u32 {%r8, %r9}, [pixelID];
|
||
|
|
cvt.u64.u32 %rd1, %r8;
|
||
|
|
cvt.u64.u32 %rd2, %r9;
|
||
|
|
@%p1 bra BB0_2;
|
||
|
|
bra.uni BB0_1;
|
||
|
|
|
||
|
|
BB0_2:
|
||
|
|
mov.u64 %rd41, image2;
|
||
|
|
cvta.global.u64 %rd18, %rd41;
|
||
|
|
mov.u32 %r19, 8;
|
||
|
|
// inline asm
|
||
|
|
call (%rd17), _rt_buffer_get_64, (%rd18, %r1, %r19, %rd1, %rd2, %rd8, %rd8);
|
||
|
|
// inline asm
|
||
|
|
ld.global.v2.u32 {%r22, %r23}, [pixelID];
|
||
|
|
cvt.u64.u32 %rd25, %r22;
|
||
|
|
cvt.u64.u32 %rd26, %r23;
|
||
|
|
// inline asm
|
||
|
|
call (%rd23), _rt_buffer_get_64, (%rd18, %r1, %r19, %rd25, %rd26, %rd8, %rd8);
|
||
|
|
// inline asm
|
||
|
|
ld.global.v2.u32 {%r26, %r27}, [pixelID];
|
||
|
|
cvt.u64.u32 %rd31, %r26;
|
||
|
|
cvt.u64.u32 %rd32, %r27;
|
||
|
|
// inline asm
|
||
|
|
call (%rd29), _rt_buffer_get_64, (%rd18, %r1, %r19, %rd31, %rd32, %rd8, %rd8);
|
||
|
|
// inline asm
|
||
|
|
ld.global.v2.u32 {%r30, %r31}, [pixelID];
|
||
|
|
cvt.u64.u32 %rd37, %r30;
|
||
|
|
cvt.u64.u32 %rd38, %r31;
|
||
|
|
mov.u64 %rd42, image3;
|
||
|
|
cvta.global.u64 %rd36, %rd42;
|
||
|
|
mov.u32 %r21, 4;
|
||
|
|
// inline asm
|
||
|
|
call (%rd35), _rt_buffer_get_64, (%rd36, %r1, %r21, %rd37, %rd38, %rd8, %rd8);
|
||
|
|
// inline asm
|
||
|
|
cvt.sat.f32.f32 %f11, %f1;
|
||
|
|
mul.f32 %f12, %f11, 0f437F0000;
|
||
|
|
cvt.rzi.u32.f32 %r34, %f12;
|
||
|
|
cvt.sat.f32.f32 %f13, %f2;
|
||
|
|
mul.f32 %f14, %f13, 0f437F0000;
|
||
|
|
cvt.rzi.u32.f32 %r35, %f14;
|
||
|
|
cvt.sat.f32.f32 %f15, %f3;
|
||
|
|
mul.f32 %f16, %f15, 0f437F0000;
|
||
|
|
cvt.rzi.u32.f32 %r36, %f16;
|
||
|
|
cvt.u16.u32 %rs8, %r36;
|
||
|
|
cvt.u16.u32 %rs9, %r35;
|
||
|
|
cvt.u16.u32 %rs10, %r34;
|
||
|
|
mov.u16 %rs11, 255;
|
||
|
|
st.v4.u8 [%rd35], {%rs10, %rs9, %rs8, %rs11};
|
||
|
|
bra.uni BB0_3;
|
||
|
|
|
||
|
|
BB0_1:
|
||
|
|
mov.u64 %rd16, image2;
|
||
|
|
cvta.global.u64 %rd11, %rd16;
|
||
|
|
mov.u32 %r13, 8;
|
||
|
|
// inline asm
|
||
|
|
call (%rd10), _rt_buffer_get_64, (%rd11, %r1, %r13, %rd1, %rd2, %rd8, %rd8);
|
||
|
|
// inline asm
|
||
|
|
mov.f32 %f7, 0f3F800000;
|
||
|
|
// inline asm
|
||
|
|
{ cvt.rn.f16.f32 %rs4, %f7;}
|
||
|
|
|
||
|
|
// inline asm
|
||
|
|
// inline asm
|
||
|
|
{ cvt.rn.f16.f32 %rs3, %f3;}
|
||
|
|
|
||
|
|
// inline asm
|
||
|
|
// inline asm
|
||
|
|
{ cvt.rn.f16.f32 %rs2, %f2;}
|
||
|
|
|
||
|
|
// inline asm
|
||
|
|
// inline asm
|
||
|
|
{ cvt.rn.f16.f32 %rs1, %f1;}
|
||
|
|
|
||
|
|
// inline asm
|
||
|
|
st.v4.u16 [%rd10], {%rs1, %rs2, %rs3, %rs4};
|
||
|
|
|
||
|
|
BB0_3:
|
||
|
|
ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
|